Wei Zhang
Orcid: 0000-0002-7622-6714Affiliations:
- Hong Kong University of Science and Technology, Department of Electronic and Computer Engineering, China
- Nanyang Technological University, Singapore (2010 - 2013)
- Princeton University, NJ, USA (PhD 2009)
According to our database1,
Wei Zhang
authored at least 185 papers
between 2005 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
IEEE Trans. Neural Networks Learn. Syst., November, 2024
Deep Reinforcement Learning-Based Power Management for Chiplet-Based Multicore Systems.
IEEE Trans. Very Large Scale Integr. Syst., September, 2024
FADO: Floorplan-Aware Directive Optimization Based on Synthesis and Analytical Models for High-Level Synthesis Designs on Multi-Die FPGAs.
ACM Trans. Reconfigurable Technol. Syst., September, 2024
AMF-Placer 2.0: Open-Source Timing-Driven Analytical Mixed-Size Placer for Large-Scale Heterogeneous FPGA.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., September, 2024
IEEE Trans. Very Large Scale Integr. Syst., August, 2024
Boosting the Convergence of Reinforcement Learning-Based Auto-Pruning Using Historical Data.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., February, 2024
Retain, Blend, and Exchange: A Quality-aware Spatial-Stereo Fusion Approach for Event Stream Recognition.
CoRR, 2024
PC-oriented Prediction-based Runtime Power Management for GPGPU using Knowledge Transfer.
Proceedings of the 36th ACM Symposium on Parallelism in Algorithms and Architectures, 2024
Proceedings of the 38th ACM International Conference on Supercomputing, 2024
LCM: LLM-focused Hybrid SPM-cache Architecture with Cache Management for Multi-Core AI Accelerators.
Proceedings of the 38th ACM International Conference on Supercomputing, 2024
GraFlex: Flexible Graph Processing on FPGAs through Customized Scalable Interconnection Network.
Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2024
A Modular Branch Predictor Performance Analysis Framework for Fast Design Space Exploration.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
Explainable Fuzzy Neural Network with Multi-Fidelity Reinforcement Learning for Micro-Architecture Design Space Exploration.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024
Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024
2023
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023
ACM Trans. Embed. Comput. Syst., November, 2023
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023
Design and Analysis of RSA and Paillier Homomorphic Cryptosystems Using PSO-Based Evolutionary Computation.
IEEE Trans. Computers, July, 2023
ACM Trans. Reconfigurable Technol. Syst., June, 2023
NeuroPDR: Integrating Neural Networks in the PDR Algorithm for Hardware Model Checking.
Proceedings of the 5th ACM/IEEE Workshop on Machine Learning for CAD, 2023
FIONA: Photonic-Electronic CoSimulation Framework and Transferable Prototyping for Photonic Accelerator.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023
DiffLo: A Graph-based Method for Functional Discrepancy Localization in High-level Synthesis.
Proceedings of the International Conference on Field Programmable Technology, 2023
FADO: Floorplan-Aware Directive Optimization for High-Level Synthesis Designs on Multi-Die FPGAs.
Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2023
Tensor-Product-Based Accelerator for Area-efficient and Scalable Number Theoretic Transform.
Proceedings of the 31st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
PertNAS: Architectural Perturbations for Memory-Efficient Neural Architecture Search.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
2022
Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems.
J. Syst. Archit., 2022
Introduction to the Special Issue on Hardware-Assisted Security for Emerging Internet of Things.
ACM J. Emerg. Technol. Comput. Syst., 2022
CoRR, 2022
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022
Proceedings of the International Conference on Field-Programmable Technology, 2022
Proceedings of the International Conference on Field-Programmable Technology, 2022
Proceedings of the Computer Vision - ECCV 2022, 2022
PowerGear: Early-Stage Power Estimation in FPGA HLS via Heterogeneous Edge-Centric GNNs.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
2021
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
Fangorn: Adaptive Execution Framework for Heterogeneous Workloads on Shared Clusters.
Proc. VLDB Endow., 2021
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021
Concentration Gradients Enhancement of Christmas-Tree Structure Based on a Look-Up Table.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021
Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021
Load-Step: A Precise TrustZone Execution Control Framework for Exploring New Side-channel Attacks Like Flush+Evict.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
2020
Optimizing OpenCL-Based CNN Design on FPGA with Comprehensive Design Space Exploration and Collaborative Performance Modeling.
ACM Trans. Reconfigurable Technol. Syst., 2020
BBB-CFI: Lightweight CFI Approach Against Code-Reuse Attacks Using Basic Block Information.
ACM Trans. Embed. Comput. Syst., 2020
Energy Minimization for Multicore Platforms Through DVFS and VR Phase Scaling With Comprehensive Convex Model.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Guest Editorial: ACM JETC Special Issue on New Trends in Nanolectronic Device, Circuit, and Architecture Design: Part 2.
ACM J. Emerg. Technol. Comput. Syst., 2020
Introduction to the Special Issue on New Trends in Nanoelectronic Device, Circuit, and Architecture Design, Part 1.
ACM J. Emerg. Technol. Comput. Syst., 2020
Proceedings of the International Conference on Neuromorphic Systems, 2020
Proceedings of the 40th IEEE International Conference on Distributed Computing Systems, 2020
Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, 2020
Boyi: A Systematic Framework for Automatically Deciding the Right Execution Model of OpenCL Applications on FPGAs.
Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020
A History-Based Auto-Tuning Framework for Fast and High-Performance DNN Design on GPU.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020
2019
IEEE Trans. Very Large Scale Integr. Syst., 2019
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019
Hi-ClockFlow: Multi-Clock Dataflow Automation and Throughput Optimization in High-Level Synthesis.
Proceedings of the International Conference on Computer-Aided Design, 2019
Poly: Efficient Heterogeneous System and Application Management for Interactive Applications.
Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture, 2019
A Hybrid Data-Consistent Framework for Link-Aware AccessManagement in Emerging CPU-FPGA Platforms.
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019
Towards Efficient and Scalable Acceleration of Online Decision Tree Learning on FPGA.
Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
LAMA: Link-Aware Hybrid Management for Memory Accesses in Emerging CPU-FPGA Platforms.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019
Real-Time Detection and Tracking Using Hybrid DNNs and Space-Aware Color Feature: From Algorithm to System.
Proceedings of the Pattern Recognition - 5th Asian Conference, 2019
2018
Scalable Light-Weight Integration of FPGA Based Accelerators with Chip Multi-Processors.
IEEE Trans. Multi Scale Comput. Syst., 2018
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
Parallelizing Hardware Tasks on Multicontext FPGA With Efficient Placement and Scheduling Algorithms.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
Thermal-Aware Task Mapping on Dynamically Reconfigurable Network-on-Chip Based Multiprocessor System-on-Chip.
IEEE Trans. Computers, 2018
IEEE Trans. Computers, 2018
Comput. Secur., 2018
SGXlinger: A New Side-Channel Attack Vector Based on Interrupt Latency Against Enclave Execution.
Proceedings of the 36th IEEE International Conference on Computer Design, 2018
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018
Proceedings of the 26th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2018
2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
A Variation-Aware Adaptive Fuzzy Control System for Thermal Management of Microprocessors.
IEEE Trans. Very Large Scale Integr. Syst., 2017
IEEE Trans. Circuits Syst. II Express Briefs, 2017
Local-to-global background modeling for moving object detection from non-static cameras.
Multim. Tools Appl., 2017
Circuits Syst. Signal Process., 2017
Circuits Syst. Signal Process., 2017
COMBA: A comprehensive model-based analysis framework for high level synthesis of real applications.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017
A novel two-stage modular multiplier based on racetrack memory for asymmetric cryptography.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017
Decision tree based hardware power monitoring for run time dynamic power management in FPGA.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017
Dynamic Partitioning for Library based Placement on Heterogeneous FPGAs (Abstract Only).
Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017
Proceedings of the 25th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2017
FP-DNN: An Automated Framework for Mapping Deep Neural Networks onto FPGAs with RTL-HLS Hybrid Templates.
Proceedings of the 25th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2017
Proceedings of the 54th Annual Design Automation Conference, 2017
No-Jump-into-Basic-Block: Enforce Basic Block CFI on the Fly for Real-world Binaries.
Proceedings of the 54th Annual Design Automation Conference, 2017
Two-stage thermal-aware scheduling of task graphs on 3D multi-cores exploiting application and architecture characteristics.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
Distributed Sensor Network-on-Chip for Performance Optimization of Soft-Error-Tolerant Multiprocessor System-on-Chip.
IEEE Trans. Very Large Scale Integr. Syst., 2016
A Fine-Grained Control Flow Integrity Approach Against Runtime Memory Attacks for Embedded Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
IEEE Trans. Parallel Distributed Syst., 2016
Library-Based Placement and Routing in FPGAs with Support of Partial Reconfiguration.
ACM Trans. Design Autom. Electr. Syst., 2016
Semantics-Based Online Malware Detection: Towards Efficient Real-Time Protection Against Malware.
IEEE Trans. Inf. Forensics Secur., 2016
Cost-efficient Acceleration of Hardware Trojan Detection Through Fan-Out Cone Analysis and Weighted Random Pattern Technique.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
J. Circuits Syst. Comput., 2016
Area Efficient Hardware Architecture for Implicitly-Defined Complex Events Processing.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016
Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
Proceedings of the Applied Reconfigurable Computing - 12th International Symposium, 2016
2015
Actively Alleviate Power Gating-Induced Power/Ground Noise Using Parasitic Capacitance of On-Chip Memories in MPSoC.
IEEE Trans. Very Large Scale Integr. Syst., 2015
FDR 2.0: A Low-Power Dynamically Reconfigurable Architecture and Its FinFET Implementation.
IEEE Trans. Very Large Scale Integr. Syst., 2015
Leveraging Hotspots and Improving Chip Reliability via Carbon Nanotube Grid Thermal Structure.
IEEE Trans. Very Large Scale Integr. Syst., 2015
Proceedings of the IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2015
Traffic-Aware Application Mapping for Network-on-Chip Based Multiprocessor System-on-Chip.
Proceedings of the 17th IEEE International Conference on High Performance Computing and Communications, 2015
An Efficient Technique for Chip Temperature Optimization of Multiprocessor Systems in the Dark Silicon Era.
Proceedings of the 17th IEEE International Conference on High Performance Computing and Communications, 2015
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015
Proceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2015
Proceedings of the Computer Vision - CCF Chinese Conference, 2015
2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
A Fine-Grain Dynamically Reconfigurable Architecture Aimed at Reducing the FPGA-ASIC Gaps.
IEEE Trans. Very Large Scale Integr. Syst., 2014
Systematic Analysis of Crosstalk Noise in Folded-Torus-Based Optical Networks-on-Chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014
IEEE Trans. Computers, 2014
On-chip sensor networks for soft-error tolerant real-time multiprocessor systems-on-chip.
ACM J. Emerg. Technol. Comput. Syst., 2014
Thermal-aware task scheduling for peak temperature minimization under periodic constraint for 3D-MPSoCs.
Proceedings of the 25nd IEEE International Symposium on Rapid System Prototyping, 2014
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014
Proceedings of the International Symposium on Intelligent Signal Processing and Communication Systems, 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Proceedings of the IEEE 3rd Global Conference on Consumer Electronics, 2014
Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014
Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014
Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014
A low cost acceleration method for hardware trojan detection based on fan-out cone analysis.
Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis, 2014
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014
Proceedings of the 2014 NASA/ESA Conference on Adaptive Hardware and Systems, 2014
2013
IEEE Trans. Very Large Scale Integr. Syst., 2013
Formal Worst-Case Analysis of Crosstalk Noise in Mesh-Based Optical Networks-on-Chip.
IEEE Trans. Very Large Scale Integr. Syst., 2013
IEEE Trans. Circuits Syst. I Regul. Pap., 2013
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013
ACM J. Emerg. Technol. Comput. Syst., 2013
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013
Active power-gating-induced power/ground noise alleviation using parasitic capacitance of on-chip memories.
Proceedings of the Design, Automation and Test in Europe, 2013
Digital-assisted noise-eliminating training for memristor crossbar-based analog neuromorphic computing engine.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
Thermal simulator of 3D-IC with modeling of anisotropic TSV conductance and microchannel entrance effects.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
2012
IEEE Trans. Very Large Scale Integr. Syst., 2012
Design Exploration of Hybrid CMOS and Memristor Circuit by New Modified Nodal Analysis.
IEEE Trans. Very Large Scale Integr. Syst., 2012
A Torus-Based Hierarchical Optical-Electronic Network-on-Chip for Multiprocessor System-on-Chip.
ACM J. Emerg. Technol. Comput. Syst., 2012
ACM J. Emerg. Technol. Comput. Syst., 2012
Design of low power 3D hybrid memory by non-volatile CBRAM-crossbar with block-level data-retention.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012
Decentralized agent based re-clustering for task mapping of tera-scale network-on-chip system.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Proceedings of the 30th International IEEE Conference on Computer Design, 2012
A thermal and process variation aware MTJ switching model and its applications in soft error analysis.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012
uBRAM-based run-time reconfigurable FPGA and corresponding reconfiguration methodology.
Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012
2011
IEEE Embed. Syst. Lett., 2011
Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011
Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011
Case study: Alleviating hotspots and improving chip reliability via carbon nanotube thermal interface.
Proceedings of the Design, Automation and Test in Europe, 2011
Proceedings of the Low-Power Variation-Tolerant Design in Nanometer Silicon, 2011
2010
ACM J. Emerg. Technol. Comput. Syst., 2010
Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures, 2010
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010
Proceedings of the 47th Design Automation Conference, 2010
2009
IEEE Micro, 2009
Design space exploration and data memory architecture design for a hybrid nano/CMOS dynamically reconfigurable architecture.
ACM J. Emerg. Technol. Comput. Syst., 2009
ACM J. Emerg. Technol. Comput. Syst., 2009
A hybrid Nano/CMOS dynamically reconfigurable system - Part II: Design optimization flow.
ACM J. Emerg. Technol. Comput. Syst., 2009
A Low-power Low-cost Optical Router for Optical Networks-on-Chip in Multiprocessor Systems-on-Chip.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009
A low-power fat tree-based optical Network-On-Chip for multiprocessor system-on-chip.
Proceedings of the Design, Automation and Test in Europe, 2009
2007
NanoMap: An Integrated Design Optimization Flow for a Hybrid Nanotube/CMOS Dynamically Reconfigurable Architecture.
Proceedings of the 44th Design Automation Conference, 2007
2006
Proceedings of the 43rd Design Automation Conference, 2006
2005
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005