Wei Zhang

IEEE Trans. Very Large Scale Integr. Syst., August, 2024

Boosting the Convergence of Reinforcement Learning-Based Auto-Pruning Using Historical Data.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., February, 2024

gem5-NVDLA: A Simulation Framework for Compiling, Scheduling, and Architecture Evaluation on AI System-on-Chips.

[BibT_eX]

[DOI]

Chengtao Lai

ACM Trans. Design Autom. Electr. Syst., 2024

Dual-AEB: Synergizing Rule-Based and Multimodal Large Language Models for Effective Emergency Braking.

[BibT_eX]

[DOI]

CoRR, 2024

Retain, Blend, and Exchange: A Quality-aware Spatial-Stereo Fusion Approach for Event Stream Recognition.

[BibT_eX]

[DOI]

CoRR, 2024

PC-oriented Prediction-based Runtime Power Management for GPGPU using Knowledge Transfer.

[BibT_eX]

[DOI]

Proceedings of the 36th ACM Symposium on Parallelism in Algorithms and Architectures, 2024

NEOCNN: NTT-Enabled Optical Convolution Neural Network Accelerator.

[BibT_eX]

[DOI]

Proceedings of the 38th ACM International Conference on Supercomputing, 2024

LCM: LLM-focused Hybrid SPM-cache Architecture with Cache Management for Multi-Core AI Accelerators.

[BibT_eX]

[DOI]

Proceedings of the 38th ACM International Conference on Supercomputing, 2024

GraFlex: Flexible Graph Processing on FPGAs through Customized Scalable Interconnection Network.

[BibT_eX]

[DOI]

Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2024

A Modular Branch Predictor Performance Analysis Framework for Fast Design Space Exploration.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

Explainable Fuzzy Neural Network with Multi-Fidelity Reinforcement Learning for Micro-Architecture Design Space Exploration.

[BibT_eX]

[DOI]

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

Accel-NASBench: Sustainable Benchmarking for Accelerator-Aware NAS.

[BibT_eX]

[DOI]

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

DeepIC3: Guiding IC3 Algorithms by Graph Neural Network Clause Prediction.

[BibT_eX]

[DOI]

Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024

2023

Accelerating Loop-Oriented RTL Simulation With Code Instrumentation.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023

Special Issue: "AI Acceleration on FPGAs".

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., November, 2023

HL-Pow: Learning-Assisted Pre-RTL Power Modeling and Optimization for FPGA HLS.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023

Design and Analysis of RSA and Paillier Homomorphic Cryptosystems Using PSO-Based Evolutionary Computation.

[BibT_eX]

[DOI]

Sathi Sarveswara Reddy

IEEE Trans. Computers, July, 2023

Introduction to the Special Issue on FPT 2021.

[BibT_eX]

[DOI]

Andreas Koch

ACM Trans. Reconfigurable Technol. Syst., June, 2023

NeuroPDR: Integrating Neural Networks in the PDR Algorithm for Hardware Model Checking.

[BibT_eX]

[DOI]

Guangyu Hu

Hongce Zhang

Proceedings of the 5th ACM/IEEE Workshop on Machine Learning for CAD, 2023

FIONA: Photonic-Electronic CoSimulation Framework and Transferable Prototyping for Photonic Accelerator.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

DiffLo: A Graph-based Method for Functional Discrepancy Localization in High-level Synthesis.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field Programmable Technology, 2023

FADO: Floorplan-Aware Directive Optimization for High-Level Synthesis Designs on Multi-Die FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2023

Tensor-Product-Based Accelerator for Area-efficient and Scalable Number Theoretic Transform.

[BibT_eX]

[DOI]

Yuying Zhang

Sathi Sarveswara Reddy

Zili Kou

Proceedings of the 31st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2023

Cache Side-channel Attacks and Defenses of the Sliding Window Algorithm in TEEs.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

PROPHET: Predictive On-Chip Power Meter in Hardware Accelerator for DNN.

[BibT_eX]

[DOI]

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

ACGraph: Accelerating Streaming Graph Processing via Dependence Hierarchy.

[BibT_eX]

[DOI]

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

PertNAS: Architectural Perturbations for Memory-Efficient Neural Architecture Search.

[BibT_eX]

[DOI]

Afzal Ahmad

Zhiyao Xie

Benjamin Chen Ming Choong

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022

Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems.

[BibT_eX]

[DOI]

J. Syst. Archit., 2022

Introduction to the Special Issue on Hardware-Assisted Security for Emerging Internet of Things.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2022

AutoCellLibX: Automated Standard Cell Library Extension Based on Pattern Mining.

[BibT_eX]

[DOI]

CoRR, 2022

Attack Directories on ARM big.LITTLE Processors.

[BibT_eX]

[DOI]

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

Message from the General Chair and Program Co-Chairs.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field-Programmable Technology, 2022

Preface.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field-Programmable Technology, 2022

Bayesian Optimization with Clustering and Rollback for CNN Auto Pruning.

[BibT_eX]

[DOI]

Hanwei Fan

Jiandong Mu

Proceedings of the Computer Vision - ECCV 2022, 2022

PowerGear: Early-Stage Power Estimation in FPGA HLS via Heterogeneous Edge-Centric GNNs.

[BibT_eX]

[DOI]

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021

Hard-ODT: Hardware-Friendly Online Decision Tree Learning Algorithm and System.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Fangorn: Adaptive Execution Framework for Heterogeneous Workloads on Shared Clusters.

[BibT_eX]

[DOI]

Proc. VLDB Endow., 2021

TCL: Transformer-based Dynamic Graph Modelling via Contrastive Learning.

[BibT_eX]

[DOI]

CoRR, 2021

AMF-Placer: High-Performance Analytical Mixed-size Placer for FPGA.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Concentration Gradients Enhancement of Christmas-Tree Structure Based on a Look-Up Table.

[BibT_eX]

[DOI]

Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

Graph Sampling with Fast Random Walker on HBM-enabled FPGA Accelerators.

[BibT_eX]

[DOI]

Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021

Load-Step: A Precise TrustZone Execution Control Framework for Exploring New Side-channel Attacks Like Flush+Evict.

[BibT_eX]

[DOI]

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020

Optimizing OpenCL-Based CNN Design on FPGA with Comprehensive Design Space Exploration and Collaborative Performance Modeling.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., 2020

BBB-CFI: Lightweight CFI Approach Against Code-Reuse Attacks Using Basic Block Information.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2020

Energy Minimization for Multicore Platforms Through DVFS and VR Phase Scaling With Comprehensive Convex Model.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Performance Modeling and Directives Optimization for High-Level Synthesis on FPGA.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Guest Editorial: ACM JETC Special Issue on New Trends in Nanolectronic Device, Circuit, and Architecture Design: Part 2.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2020

Introduction to the Special Issue on New Trends in Nanoelectronic Device, Circuit, and Architecture Design, Part 1.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2020

NCPower: Power Modelling for NVM-based Neuromorphic Chip.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Neuromorphic Systems, 2020

Energy Efficient In-memory Integer Multiplication Based on Racetrack Memory.

[BibT_eX]

[DOI]

Proceedings of the 40th IEEE International Conference on Distributed Computing Systems, 2020

FP-Stereo: Hardware-Efficient Stereo Vision for Embedded Applications.

[BibT_eX]

[DOI]

Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, 2020

Boyi: A Systematic Framework for Automatically Deciding the Right Execution Model of OpenCL Applications on FPGAs.

[BibT_eX]

[DOI]

Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020

A History-Based Auto-Tuning Framework for Fast and High-Performance DNN Design on GPU.

[BibT_eX]

[DOI]

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

iGPU Leak: An Information Leakage Vulnerability on Intel Integrated GPU.

[BibT_eX]

[DOI]

Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

HL-Pow: A Learning-Based Power Modeling Framework for High-Level Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019

Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory.

[BibT_eX]

[DOI]

Ibrahim Abe M. Elfadel

Mehran Mozaffari Kermani

IEEE Trans. Very Large Scale Integr. Syst., 2019

An Ensemble Learning Approach for In-Situ Monitoring of FPGA Dynamic Power.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

A Cost-Effective CNN Accelerator Design with Configurable PU on FPGA.

[BibT_eX]

[DOI]

Chi Fung Brian Fong

Jiandong Mu

Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

Hi-ClockFlow: Multi-Clock Dataflow Automation and Throughput Optimization in High-Level Synthesis.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer-Aided Design, 2019

Poly: Efficient Heterogeneous System and Application Management for Interactive Applications.

[BibT_eX]

[DOI]

Shuo Wang

Yun Liang

Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture, 2019

A Hybrid Data-Consistent Framework for Link-Aware AccessManagement in Emerging CPU-FPGA Platforms.

[BibT_eX]

[DOI]

Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

Towards Efficient and Scalable Acceleration of Online Decision Tree Learning on FPGA.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019

Machine Learning Based Routing Congestion Prediction in FPGA High-Level Synthesis.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

LAMA: Link-Aware Hybrid Management for Memory Accesses in Emerging CPU-FPGA Platforms.

[BibT_eX]

[DOI]

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Accelerate pattern recognition for cyber security analysis.

[BibT_eX]

[DOI]

Mohammad Tahghighi

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

Real-Time Detection and Tracking Using Hybrid DNNs and Space-Aware Color Feature: From Algorithm to System.

[BibT_eX]

[DOI]

Proceedings of the Pattern Recognition - 5th Asian Conference, 2019

2018

Scalable Light-Weight Integration of FPGA Based Accelerators with Chip Multi-Processors.

[BibT_eX]

[DOI]

IEEE Trans. Multi Scale Comput. Syst., 2018

Hi-DMM: High-Performance Dynamic Memory Management in High-Level Synthesis.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Parallelizing Hardware Tasks on Multicontext FPGA With Efficient Placement and Scheduling Algorithms.

[BibT_eX]

[DOI]

Hao Liang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Thermal-Aware Task Mapping on Dynamically Reconfigurable Network-on-Chip Based Multiprocessor System-on-Chip.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2018

FlexCL: A Model of Performance and Power for OpenCL Workloads on FPGAs.

[BibT_eX]

[DOI]

Yun Liang

Shuo Wang

IEEE Trans. Computers, 2018

ROPSentry: Runtime defense against ROP attacks using hardware performance counters.

[BibT_eX]

[DOI]

Bihuan Chen

Mahinthan Chandramohan

Comput. Secur., 2018

SGXlinger: A New Side-Channel Attack Vector Based on Interrupt Latency Against Enclave Execution.

[BibT_eX]

[DOI]

Proceedings of the 36th IEEE International Conference on Computer Design, 2018

A Collaborative Framework for FPGA-based CNN Design Modeling and Optimization.

[BibT_eX]

[DOI]

Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

CAMAS: Static and Dynamic Hybrid Cache Management for CPU-FPGA Platforms.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2018

2017

Multikernel Data Partitioning With Channel on OpenCL-Based FPGAs.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

A Variation-Aware Adaptive Fuzzy Control System for Thermal Management of Microprocessors.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

Editorial.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

A Hybrid Logic Block Architecture in FPGA for Holistic Efficiency.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2017

Local-to-global background modeling for moving object detection from non-static cameras.

[BibT_eX]

[DOI]

Multim. Tools Appl., 2017

Pipeline Reconfigurable DSP for Dynamically Reconfigurable Architectures.

[BibT_eX]

[DOI]

Rakesh Warrier

Circuits Syst. Signal Process., 2017

Fracturable DSP Block for Multi-context Reconfigurable Architectures.

[BibT_eX]

[DOI]

Circuits Syst. Signal Process., 2017

HeteroSim: A Heterogeneous CPU-FPGA Simulator.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2017

COMBA: A comprehensive model-based analysis framework for high level synthesis of real applications.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

A novel two-stage modular multiplier based on racetrack memory for asymmetric cryptography.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

A hybrid approach to cache management in heterogeneous CPU-FPGA platforms.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Decision tree based hardware power monitoring for run time dynamic power management in FPGA.

[BibT_eX]

[DOI]

Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

PAAS: A system level simulator for heterogeneous computing architectures.

[BibT_eX]

[DOI]

Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

Dynamic Partitioning for Library based Placement on Heterogeneous FPGAs (Abstract Only).

[BibT_eX]

[DOI]

Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017

Dynamic Module Partitioning for Library Based Placement on Heterogeneous FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2017

FP-DNN: An Automated Framework for Mapping Deep Neural Networks onto FPGAs with RTL-HLS Hybrid Templates.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2017

FlexCL: An Analytical Performance Model for OpenCL Workloads on Flexible FPGAs.

[BibT_eX]

[DOI]

Shuo Wang

Yun Liang

Proceedings of the 54th Annual Design Automation Conference, 2017

No-Jump-into-Basic-Block: Enforce Basic Block CFI on the Fly for Real-world Binaries.

[BibT_eX]

[DOI]

Proceedings of the 54th Annual Design Automation Conference, 2017

Two-stage thermal-aware scheduling of task graphs on 3D multi-cores exploiting application and architecture characteristics.

[BibT_eX]

[DOI]

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016

Low-Power FPGA Design Using Memoization-Based Approximate Computing.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

Distributed Sensor Network-on-Chip for Performance Optimization of Soft-Error-Tolerant Multiprocessor System-on-Chip.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

A Fine-Grained Control Flow Integrity Approach Against Runtime Memory Attacks for Embedded Systems.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

Decentralized Thermal-Aware Task Scheduling for Large-Scale Many-Core Systems.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

Melia: A MapReduce Framework on OpenCL-Based FPGAs.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2016

Library-Based Placement and Routing in FPGAs with Support of Partial Reconfiguration.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2016

Semantics-Based Online Malware Detection: Towards Efficient Real-Time Protection Against Malware.

[BibT_eX]

[DOI]

Mahinthan Chandramohan

IEEE Trans. Inf. Forensics Secur., 2016

Cost-efficient Acceleration of Hardware Trojan Detection Through Fan-Out Cone Analysis and Weighted Random Pattern Technique.

[BibT_eX]

[DOI]

Bin Zhou

Jason Teo Kian Jin

Vivek Chaturvedi

Tao Luo

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Thermal-Aware Task Scheduling for 3D-Network-on-Chip: A Bottom to Top Scheme.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2016

Area Efficient Hardware Architecture for Implicitly-Defined Complex Events Processing.

[BibT_eX]

[DOI]

Mohammad Tahghighi

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Online malware defense using attack behavior model.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

A performance analysis framework for optimizing OpenCL applications on FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016

Modular Placement for Interposer based Multi-FPGA Systems.

[BibT_eX]

[DOI]

Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

Relational query processing on OpenCL-based FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

Accelerating Database Query Processing on OpenCL-based FPGAs (Abstract Only).

[BibT_eX]

[DOI]

Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

A discrete thermal controller for chip-multiprocessors.

[BibT_eX]

[DOI]

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

A racetrack memory based in-memory booth multiplier for cryptography application.

[BibT_eX]

[DOI]

Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

Analytical Delay Model for CPU-FPGA Data Paths in Programmable System-on-Chip FPGA.

[BibT_eX]

[DOI]

Mohammad Tahghighi

Proceedings of the Applied Reconfigurable Computing - 12th International Symposium, 2016

2015

Actively Alleviate Power Gating-Induced Power/Ground Noise Using Parasitic Capacitance of On-Chip Memories in MPSoC.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

FDR 2.0: A Low-Power Dynamically Reconfigurable Architecture and Its FinFET Implementation.

[BibT_eX]

[DOI]

Ting-Jung Lin

IEEE Trans. Very Large Scale Integr. Syst., 2015

Leveraging Hotspots and Improving Chip Reliability via Carbon Nanotube Grid Thermal Structure.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

Hierarchical Library Based Power Estimator for Versatile FPGAs.

[BibT_eX]

[DOI]

Proceedings of the IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2015

Traffic-Aware Application Mapping for Network-on-Chip Based Multiprocessor System-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE International Conference on High Performance Computing and Communications, 2015

An Efficient Technique for Chip Temperature Optimization of Multiprocessor Systems in the Dark Silicon Era.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE International Conference on High Performance Computing and Communications, 2015

A study of data partitioning on OpenCL-based FPGAs.

[BibT_eX]

[DOI]

Ze-ke Wang

Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

Hierarchical library based power estimator for versatile FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

Static hardware task placement on multi-context FPGA using hybrid genetic algorithm.

[BibT_eX]

[DOI]

Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

Improving Data Partitioning Performance on OpenCL-Based FPGAs.

[BibT_eX]

[DOI]

Ze-ke Wang

Proceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2015

Motion Compensation Based Fast Moving Object Detection in Dynamic Background.

[BibT_eX]

[DOI]

Proceedings of the Computer Vision - CCF Chinese Conference, 2015

2014

UNION: A Unified Inter/Intrachip Optical Network for Chip Multiprocessors.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2014

Nonvolatile CBRAM-Crossbar-Based 3-D-Integrated Hybrid Memory for Data Retention.

[BibT_eX]

[DOI]

Yuhao Wang

IEEE Trans. Very Large Scale Integr. Syst., 2014

A Fine-Grain Dynamically Reconfigurable Architecture Aimed at Reducing the FPGA-ASIC Gaps.

[BibT_eX]

[DOI]

Ting-Jung Lin

IEEE Trans. Very Large Scale Integr. Syst., 2014

Systematic Analysis of Crosstalk Noise in Folded-Torus-Based Optical Networks-on-Chip.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Floorplan Optimization of Fat-Tree-Based Networks-on-Chip for Chip Multiprocessors.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2014

On-chip sensor networks for soft-error tolerant real-time multiprocessor systems-on-chip.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2014

Thermal-aware task scheduling for peak temperature minimization under periodic constraint for 3D-MPSoCs.

[BibT_eX]

[DOI]

Vivek Chaturvedi

Amit Kumar Singh

Proceedings of the 25nd IEEE International Symposium on Rapid System Prototyping, 2014

Reconfigurable Dynamic Trusted Platform Module for Control Flow Checking.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Sum of products: Computation using modular thermometer codes.

[BibT_eX]

[DOI]

A. Benjamin Premkumar

Proceedings of the International Symposium on Intelligent Signal Processing and Communication Systems, 2014

Reconfigurable DSP block design for dynamically reconfigurable architecture.

[BibT_eX]

[DOI]

Rakesh Warrier

Hao Liang

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A low-power pipelined MAC architecture using Baugh-Wooley based multiplier.

[BibT_eX]

[DOI]

Rakesh Warrier

Proceedings of the IEEE 3rd Global Conference on Consumer Electronics, 2014

Towards automatic partial reconfiguration in FPGAs.

[BibT_eX]

[DOI]

Fubing Mao

Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014

BMP: a fast B*-tree based modular placer for FPGAs (abstract only).

[BibT_eX]

[DOI]

Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

Hierarchical library-based power estimator for versatile FPGAs (abstract only).

[BibT_eX]

[DOI]

Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

A low cost acceleration method for hardware trojan detection based on fan-out cone analysis.

[BibT_eX]

[DOI]

Bin Zhou

J. K. J. Teo

Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis, 2014

An extended framework for worst-case throughput analysis with router constraint.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

Soft error mitigation through selection of noninvert implication paths.

[BibT_eX]

[DOI]

Bin Zhou

Proceedings of the 2014 NASA/ESA Conference on Adaptive Hardware and Systems, 2014

2013

System-Level Modeling and Analysis of Thermal Effects in Optical Networks-on-Chip.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2013

Formal Worst-Case Analysis of Crosstalk Noise in Mesh-Based Optical Networks-on-Chip.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2013

A New RNS based DA Approach for Inner Product Computation.

[BibT_eX]

[DOI]

A. Benjamin Premkumar

IEEE Trans. Circuits Syst. I Regul. Pap., 2013

3-D Mesh-Based Optical Network-on-Chip for Multiprocessor System-on-Chip.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

NBTI-aware circuit node criticality computation.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2013

A hardware security scheme for RRAM-based FPGA.

[BibT_eX]

[DOI]

Yi-Chung Chen

Hai (Helen) Li

Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

Active power-gating-induced power/ground noise alleviation using parasitic capacitance of on-chip memories.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

Digital-assisted noise-eliminating training for memristor crossbar-based analog neuromorphic computing engine.

[BibT_eX]

[DOI]

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Thermal simulator of 3D-IC with modeling of anisotropic TSV conductance and microchannel entrance effects.

[BibT_eX]

[DOI]

Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012

SRAM-Based NATURE: A Dynamically Reconfigurable FPGA Based on 10T Low-Power SRAMs.

[BibT_eX]

[DOI]

Ting-Jung Lin

IEEE Trans. Very Large Scale Integr. Syst., 2012

Design Exploration of Hybrid CMOS and Memristor Circuit by New Modified Nodal Analysis.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2012

A Torus-Based Hierarchical Optical-Electronic Network-on-Chip for Multiprocessor System-on-Chip.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2012

A physical design tool for carbon nanotube field-effect transistor circuits.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2012

Design of low power 3D hybrid memory by non-volatile CBRAM-crossbar with block-level data-retention.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Low Power Electronics and Design, 2012

Decentralized agent based re-clustering for task mapping of tera-scale network-on-chip system.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A novel peripheral circuit for RRAM-based LUT.

[BibT_eX]

[DOI]

Yi-Chung Chen

Hai Li

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Distributed thermal-aware task scheduling for 3D Network-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the 30th International IEEE Conference on Computer Design, 2012

A thermal and process variation aware MTJ switching model and its applications in soft error analysis.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

uBRAM-based run-time reconfigurable FPGA and corresponding reconfiguration methodology.

[BibT_eX]

[DOI]

Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

Non-volatile 3D stacking RRAM-based FPGA.

[BibT_eX]

[DOI]

Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

A Look Up Table design with 3D bipolar RRAMs.

[BibT_eX]

[DOI]

Yi-Chung Chen

Hai Li

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

Fine-grained dynamic voltage scaling on OLED display.

[BibT_eX]

[DOI]

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011

Coroutine-Based Synthesis of Efficient Embedded Software From SystemC Models.

[BibT_eX]

[DOI]

IEEE Embed. Syst. Lett., 2011

NEMS based thermal management for 3D many-core system.

[BibT_eX]

[DOI]

Xiwei Huang

Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011

3D-HIM: A 3D High-density Interleaved Memory for bipolar RRAM design.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011

Modeling and Analysis of Thermal Effects in Optical Networks-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

A NoC Traffic Suite Based on Real Applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

A Hardware-Software Collaborated Method for Soft-Error Tolerant MPSoC.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

Case study: Alleviating hotspots and improving chip reliability via carbon nanotube thermal interface.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2011

Power Dissipation.

[BibT_eX]

[DOI]

James Williamson

Proceedings of the Low-Power Variation-Tolerant Design in Nanometer Silicon, 2011

2010

Low-power 3D nano/CMOS hybrid dynamically reconfigurable architecture.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2010

UNION: A unified inter/intra-chip optical network for chip multiprocessors.

[BibT_eX]

[DOI]

Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures, 2010

A Hierarchical Hybrid Optical-Electronic Network-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

Crosstalk noise and bit error rate analysis for optical network-on-chip.

[BibT_eX]

[DOI]

Proceedings of the 47th Design Automation Conference, 2010

2009

Double-Data-Rate, Wave-Pipelined Interconnect for Asynchronous NoCs.

[BibT_eX]

[DOI]

Jiang Xu

Wayne H. Wolf

IEEE Micro, 2009

Design space exploration and data memory architecture design for a hybrid nano/CMOS dynamically reconfigurable architecture.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2009

A hybrid nano/CMOS dynamically reconfigurable system - Part I: Architecture.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2009

A hybrid Nano/CMOS dynamically reconfigurable system - Part II: Design optimization flow.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2009

A Low-power Low-cost Optical Router for Optical Networks-on-Chip in Multiprocessor Systems-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

A low-power fat tree-based optical Network-On-Chip for multiprocessor system-on-chip.

[BibT_eX]

[DOI]

Huaxi Gu

Jiang Xu

Proceedings of the Design, Automation and Test in Europe, 2009

2007

NanoMap: An Integrated Design Optimization Flow for a Hybrid Nanotube/CMOS Dynamically Reconfigurable Architecture.

[BibT_eX]

[DOI]

Proceedings of the 44th Design Automation Conference, 2007

2006

NATURE: a hybrid nanotube/CMOS dynamically reconfigurable architecture.

[BibT_eX]

[DOI]

Proceedings of the 43rd Design Automation Conference, 2006

2005

ALLCN: An Automatic Logic-to-Layout Tool for Carbon Nanotube Based Nanotechnology.

[BibT_eX]

[DOI]