Wei Wei

Affiliations:
  • Northeastern University, Boston, MA, USA


According to our database1, Wei Wei authored at least 9 papers between 2011 and 2016.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2016
A Novel Scheme for Tolerating Single Event/Multiple Bit Upsets (SEU/MBU) in Non-Volatile Memories.
IEEE Trans. Computers, 2016

Design and Comparative Evaluation of a Hybrid Cache Memory at Architectural Level.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

2015
Novel Designs of Embedded Hybrid Cells for High Performance Memory Circuits.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

2014
Robust HSPICE modeling of a single electron turnstile.
Microelectron. J., 2014

New 4T-based DRAM cell designs.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

Designs and analysis of non-volatile memory cells for single event upset (SEU) tolerance.
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

2013
Extending Non-Volatile Operation to DRAM Cells.
IEEE Access, 2013

2012
Modeling a single electron turnstile in HSPICE.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

2011
A hybrid memory cell using Single-Electron transfer.
Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011


  Loading...