Wei Li
Orcid: 0000-0001-9177-4551Affiliations:
- Fudan University, State Key Lab of ASIC & System, Shanghai, China
- Ghent University, Belgium (PhD 2001)
According to our database1,
Wei Li
authored at least 45 papers
between 1998 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
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Bibliography
2024
Enhanced-Linearity Wideband Full-Duplex Receiver With Shared Self-Interference Canceller.
IEEE Trans. Very Large Scale Integr. Syst., September, 2024
Analysis and Calibration of Bit Weights in SAR and Pipelined SAR ADCs Based on Code Distribution.
IEEE Trans. Very Large Scale Integr. Syst., June, 2024
A Wideband Full-Duplex Receiver With Multi-Domain Self-Interference Cancellation Based on Capacitor Stacking Delay and Delay Compensation in Cancellers.
IEEE J. Solid State Circuits, June, 2024
A Wideband Sliding Digital-IF Quadrature Digital Transmitter for Multimode NB-IoT/BLE Applications.
IEEE J. Solid State Circuits, May, 2024
2023
A Tri-Mode Reconfigurable Receiver for GNSS/NB-IoT/BLE With 68-dB HR3 and 60-dB IMRR in 28-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst., August, 2023
A 0.7-to-2.5GHz Sliding Digital-IF Quadrature Digital Transmitter Achieving >40% System Efficiency for Multi-Mode NB-IoT/BLE Applications.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
A 12.1-16.5GHz Resistance Self-biased Inverse Class-F23 VCO Achieving 20-54kHz 1/f<sup>3</sup> Corner Frequency.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
2021
A 0.2~3.8-GHz Full-Duplex Receiver With More Than 25 dB Self-Interference Cancellation Using a C-DAC-Based Vector Canceller.
IEEE Access, 2021
Proceedings of the 14th IEEE International Conference on ASIC, 2021
A 0.9V 0.1-4GHz LNTA in 28-nm CMOS Achieving +11.3dBm IIP3 With Self-loaded Linearization Technique.
Proceedings of the 14th IEEE International Conference on ASIC, 2021
2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
2019
A 65 nm 19.1-to-20.4 GHz Sigma-Delta Fractional-N Frequency Synthesizer with Two-Point Modulation for FMCW Radar Applications.
IEICE Trans. Electron., 2019
Proceedings of the 13th IEEE International Conference on ASIC, 2019
Proceedings of the 13th IEEE International Conference on ASIC, 2019
2018
IEEE Trans. Circuits Syst. II Express Briefs, 2018
2017
A programmable divider with extended division range for 24GHz FMCW frequency synthesizer.
Proceedings of the 12th IEEE International Conference on ASIC, 2017
2015
A Monolithic Sub-sampling PLL based 6-18 GHz Frequency Synthesizer for C, X, Ku Band Communication.
IEICE Trans. Electron., 2015
IEICE Trans. Inf. Syst., 2015
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
2014
IEICE Electron. Express, 2014
2013
A Dividerless PLL With Low Power and Low Reference Spur by Aperture-Phase Detector and Phase-to-Analog Converter.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013
IEICE Electron. Express, 2013
2012
A 2.4GHz to 3.86GHz digitally controlled oscillator with 18.5kHz frequency resolution using single PMOS varactor.
IEICE Electron. Express, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
2011
A Frequency Synthesizer With Optimally Coupled QVCO and Harmonic-Rejection SSBmixer for Multi-Standard Wireless Receiver.
IEEE J. Solid State Circuits, 2011
A 22-mW 2.2%-EVM UWB Transmitter Using On-Chip Transformer and LO Leakage Calibration.
IEICE Trans. Electron., 2011
IEICE Electron. Express, 2011
Sci. China Inf. Sci., 2011
Sci. China Inf. Sci., 2011
A dual-mode VCO based low-power synthesizer with optimized automatic frequency calibration for software-defined radio.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
A harmonic-suppressed regenerative divide-by-5 frequency divider for UWB applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
A 2.1-GHz PLL with -80dBc/-74dBc reference spur based on aperture-phase detector and phase-to-analog converter.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011
2010
A fractional-N frequency synthesizer for cellular and short range multi-standard wireless receiver.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
A sideband-suppressed low-power synthesizer for 14-band dual-carrier MB-OFDM UWB transceivers.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
2006
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
2004
A Formal Framework of UML.
Proceedings of the International Conference on Software Engineering Research and Practice, 2004
2003
Low-frequency electronic gate detection for the counting and sizing of cells, bacteria, and colloidal particles in liquids.
IEEE Trans. Instrum. Meas., 2003
2000
Practical design considerations on lumped element filters for microwave applications.
Proceedings of the 2000 7th IEEE International Conference on Electronics, 2000
1998
Proceedings of the Broadband Communications: The future of telecommunications, 1998