Wei-Kai Cheng

According to our database, Wei-Kai Cheng authored at least 24 papers between 1994 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2024

Automated Quantization Strategy on CIM.

Yu-Shan Huang, Wei-Kai Cheng

Proceedings of the International Conference on Consumer Electronics - Taiwan, 2024

Impact of ADC Bits on CNNs in CIM Architecture.

Chia-Hsuan Chang, Wei-Kai Cheng

Proceedings of the International Conference on Consumer Electronics - Taiwan, 2024

2023

Framework and Quantization Method Design for CIM.

Hsin-Yi Pai, Wei-Kai Cheng

Proceedings of the International Conference on Consumer Electronics - Taiwan, 2023

Convolutional Neural Network Accelerator for Integrated Winograd and Convolution Computations.

Yueh-Fan Lo, Wei-Kai Cheng

Proceedings of the International Conference on Consumer Electronics - Taiwan, 2023

2022

Layer-wise Exploration of Synaptic Array and Weight Mapping on Heterogeneous Tile-based RRAM CIM Architecture.

Hsin-Tzu Wu, Hsin-Yi Pai, Wei-Kai Cheng

Proceedings of the 19th International SoC Design Conference, 2022

2020

Co-Optimization of Grid-Based TAM Wire Routing and Test Scheduling with Reconfigurable Wrappers.

Jui-Hung Hung, Shih-Hsu Huang, Chun-Hua Cheng, Hsu-Yu Kao, Wei-Kai Cheng

Proceedings of the 38th IEEE VLSI Test Symposium, 2020

Architecture Design of Overlap-Add FFT on the Convolution Neural Networks.

Wei-Kai Cheng, Yuan-Chih Lo, Hsia-Tsung Wang

Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2020

Dataflow Design of Overlap-Add FFT on the Convolution Neural Networks.

Wei-Kai Cheng, Xiang-Yi Liu, Tsai-Yu Tsai

Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2020

2019

Machine Learning Techniques for Building and Evaluation of Routability-driven Macro Placement.

Wei-Kai Cheng, Chih-Shuan Wu

Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2019

2018

An Effective Approach for Building Low-Power General Activity-Driven Clock Trees.

Chen-Hsien Lin, Shih-Hsu Huang, Wei-Kai Cheng

Proceedings of the International SoC Design Conference, 2018

Integration of Retention-aware Refresh and BISR Techniques for DRAM Refresh Power Reduction.

Wei-Kai Cheng, Jian-Kai Chen, Shih-Hsu Huang

Proceedings of the International SoC Design Conference, 2018

2016

Architecture and data migration methodology for L1 cache design with hybrid SRAM and volatile STT-RAM configuration.

Wei-Kai Cheng, Yen-Heng Ciou, Po-Yuan Shen

Microprocess. Microsystems, 2016

Unified approach for simultaneous functional and timing ECO.

Jui-Hung Hung, Yu-Cheng Lin, Wei-Kai Cheng, Tsai-Ming Hsieh

IET Circuits Devices Syst., 2016

Non-Uniform Clock Mesh Synthesis with Clock Gating and Register Clustering.

Wei-Kai Cheng, Jui-Hung Hung, Yi-Hsuan Chiu

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016

Top-level activity-driven clock tree synthesis with clock skew variation considered.

Te-Jui Wang, Shih-Hsu Huang, Wei-Kai Cheng, Yih-Chih Chou

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015

A Skew-Window based Methodology for Timing Fixing in Multiple Power Modes.

Wei-Kai Cheng, Po-Han Wu, Yi-Hsuan Chiu

J. Inf. Sci. Eng., 2015

A logic difference generator with spare cells consideration for ECO synthesis.

Jui-Hung Hung, Yu-Cheng Lin, Wei-Kai Cheng, Tsai-Ming Hsieh

Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

2014

A Data Migration Approach for L1 Cache Design with SRAM and Volatile STT-RAM.

Wei-Kai Cheng, Yen-Heng Ciou

Proceedings of the Intelligent Systems and Applications, 2014

2012

A 3D IC designs partitioning algorithm with power consideration.

Ho-lin Chang, Hsiang-Cheng Lai, Tsu-Yun Hsueh, Wei-Kai Cheng, Mely Chen Chi

Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

Memory binding and layer assignment for high-level synthesis of 3D ICs.

Yi-Chun Yen, Jhih-Kai Yang, Wei-Kai Cheng

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

1999

Code generation of nested loops for DSP processors with heterogeneous registers and structural pipelining.

Wei-Kai Cheng, Youn-Long Lin

ACM Trans. Design Autom. Electr. Syst., 1999

1998

Addressing Optimization for Loop Execution Targeting DSP with Auto-Increment/Decrement Architecture.

Wei-Kai Cheng, Youn-Long Lin

Proceedings of the 11th International Symposium on System Synthesis, 1998

1995

A Transformation-Based Approach for Storage Optimization.

Wei-Kai Cheng, Youn-Long Lin

Proceedings of the 32st Conference on Design Automation, 1995

1994

Code generation for a DSP processor.

Wei-Kai Cheng, Youn-Long Lin

Proceedings of the 7th International Symposium on High Level Synthesis, 1994