Wei-Hsiang Ho
Orcid: 0000-0003-4243-0247
According to our database1,
Wei-Hsiang Ho
authored at least 3 papers
between 2017 and 2021.
Collaborative distances:
Collaborative distances:
Timeline
2017
2018
2019
2020
2021
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Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2021
A 32 Gb/s PAM-4 Optical Transceiver With Active Back Termination in 40 nm CMOS Technology.
IEEE Open J. Circuits Syst., 2021
2019
A 25-Gb/s, 2.1-pJ/bit, Fully Integrated Optical Receiver With a Baud-Rate Clock and Data Recovery.
IEEE J. Solid State Circuits, 2019
2017
A Low-Voltage PLL Design Using a New Calibration Technique for Low-Power Implantable Biomedical Systems.
Circuits Syst. Signal Process., 2017