Wei He

According to our database, Wei He authored at least 28 papers between 2011 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

HQsFL: A Novel Training Strategy for Constructing High-performance and Quantum-safe Federated Learning.

Bo Yu, Huajie Shen, Qian Xu, Wei He, Wankui Mao, Qing Zhang, Fan Zhang

Proceedings of the 19th ACM Asia Conference on Computer and Communications Security, 2024

2022

PipeFL: Hardware/Software co-Design of an FPGA Accelerator for Federated Learning.

Zixiao Wang, Biyao Che, Liang Guo, Yang Du, Ying Chen, Jizhuang Zhao, Wei He

IEEE Access, 2022

2021

Pushing the Limit of PFA: Enhanced Persistent Fault Analysis on Block Ciphers.

Guorui Xu, Fan Zhang, Bolin Yang, Xinjie Zhao, Wei He, Kui Ren

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

2020

Side-Channel Analysis and Countermeasure Design on ARM-Based Quantum-Resistant SIKE.

Fan Zhang, Bolin Yang, Xiaofei Dong, Sylvain Guilley, Zhe Liu, Wei He, Fangguo Zhang, Kui Ren

IEEE Trans. Computers, 2020

2018

Persistent Fault Analysis on Block Ciphers.

Fan Zhang, Xiaoxuan Lou, Xinjie Zhao, Shivam Bhasin, Wei He, Ruyi Ding, Samiya Qureshi, Kui Ren

IACR Trans. Cryptogr. Hardw. Embed. Syst., 2018

The Conflicted Usage of RLUTs for Security-Critical Applications on FPGA.

Debapriya Basu Roy, Shivam Bhasin, Jean-Luc Danger, Sylvain Guilley, Wei He, Debdeep Mukhopadhyay, Zakaria Najm, Xuan Thuy Ngo

J. Hardw. Syst. Secur., 2018

2017

Stealthy Hardware Trojan Based Algebraic Fault Analysis of HIGHT Block Cipher.

Hao Chen, Tao Wang, Fan Zhang, Xinjie Zhao, Wei He, Lumin Xu, Yunfei Ma

Secur. Commun. Networks, 2017

Attacks in Reality: the Limits of Concurrent Error Detection Codes Against Laser Fault Injection.

Jakub Breier, Wei He, Dirmanto Jap, Shivam Bhasin, Anupam Chattopadhyay

J. Hardw. Syst. Secur., 2017

Extensive Laser Fault Injection Profiling of 65 nm FPGA.

Jakub Breier, Wei He, Shivam Bhasin, Dirmanto Jap, Samuel Chef, Hock Guan Ong, Chee Lip Gan

J. Hardw. Syst. Secur., 2017

Low-cost design of stealthy hardware trojan for bit-level fault attacks on block ciphers.

Fan Zhang, Xinjie Zhao, Wei He, Shivam Bhasin, Shize Guo

Sci. China Inf. Sci., 2017

Transistor level SCA-resistant scheme based on fluctuating power logic.

Liang Geng, Fan Zhang, Jizhong Shen, Wei He, Shivam Bhasin, Xinjie Zhao, Shize Guo

Sci. China Inf. Sci., 2017

An electromagnetic fault injection sensor using Hogge phase-detector.

Jakub Breier, Shivam Bhasin, Wei He

Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

An FPGA-compatible PLL-based sensor against fault injection attack.

Wei He, Jakub Breier, Shivam Bhasin, Noriyuki Miura, Makoto Nagata

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016

Comprehensive Laser Sensitivity Profiling and Data Register Bit-Flips for Cryptographic Fault Attacks in 65 Nm FPGA.

Wei He, Jakub Breier, Shivam Bhasin, Dirmanto Jap, Hock Guan Ong, Chee Lip Gan

Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2016

Cheap and Cheerful: A Low-Cost Digital Sensor for Detecting Laser Fault Injection Attacks.

Wei He, Jakub Breier, Shivam Bhasin

Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2016

Ring Oscillator under Laser: Potential of PLL-based Countermeasure against Laser Fault Injection.

Wei He, Jakub Breier, Shivam Bhasin, Noriyuki Miura, Makoto Nagata

Proceedings of the 2016 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2016

PLL to the rescue: a novel EM fault countermeasure.

Noriyuki Miura, Zakaria Najm, Wei He, Shivam Bhasin, Xuan Thuy Ngo, Makoto Nagata, Jean-Luc Danger

Proceedings of the 53rd Annual Design Automation Conference, 2016

Bypassing Parity Protected Cryptography using Laser Fault Injection in Cyber-Physical System.

Wei He, Jakub Breier, Shivam Bhasin, Anupam Chattopadhyay

Proceedings of the 2nd ACM International Workshop on Cyber-Physical System Security, 2016

Supervised and unsupervised machine learning for side-channel based Trojan detection.

Dirmanto Jap, Wei He, Shivam Bhasin

Proceedings of the 27th IEEE International Conference on Application-specific Systems, 2016

2015

Exploiting FPGA Block Memories for Protected Cryptographic Implementations.

Shivam Bhasin, Jean-Luc Danger, Sylvain Guilley, Wei He

ACM Trans. Reconfigurable Technol. Syst., 2015

Sophisticated security verification on routing repaired balanced cell-based dual-rail logic against side channel analysis.

Wei He, Shivam Bhasin, Andrés Otero, Tarik Graba, Eduardo de la Torre, Jean-Luc Danger

IET Inf. Secur., 2015

Process Variation Evaluation Using RO PUF for Enhancing SCA-Resistant Dual-Rail Implementation.

Wei He, Dirmanto Jap, Alexander Herrmann

Proceedings of the Information Security Applications - 16th International Workshop, 2015

Multiple Fault Attack on PRESENT with a Hardware Trojan Implementation in FPGA.

Jakub Breier, Wei He

Proceedings of the 2015 International Workshop on Secure Internet of Things, 2015

Dual-rail active protection system against side-channel analysis in FPGAs.

Wei He, Dirmanto Jap

Proceedings of the 26th IEEE International Conference on Application-specific Systems, 2015

2014

Customized and automated routing repair toolset towards side-channel analysis resistant dual rail logic.

Wei He, Andrés Otero, Eduardo de la Torre, Teresa Riesgo

Microprocess. Microsystems, 2014

2012

Automatic generation of identical routing pairs for FPGA implemented DPL logic.

Wei He, Andrés Otero, Eduardo de la Torre, Teresa Riesgo

Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012

An Interleaved EPE-Immune PA-DPL Structure for Resisting Concentrated EM Side Channel Attacks on FPGA Implementation.

Wei He, Eduardo de la Torre, Teresa Riesgo

Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2012

2011

A Precharge-Absorbed DPL Logic for Reducing Early Propagation Effects on FPGA Implementations.

Wei He, Eduardo de la Torre, Teresa Riesgo

Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011