Wei Han
Affiliations:- University of Edinburgh, School of Engineering, UK
According to our database1,
Wei Han
authored at least 14 papers
between 2005 and 2009.
Collaborative distances:
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Bibliography
2009
Multicore Architectures With Dynamically Reconfigurable Array Processors for Wireless Broadband Technologies.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009
Heterogeneous multi-core architectures with dynamically reconfigurable processors for WiMAX transmitter.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009
Heterogeneous multi-core architectures with dynamically reconfigurable processors for wireless communication.
Proceedings of the IEEE 7th Symposium on Application Specific Processors, 2009
Proceedings of the Design, Automation and Test in Europe, 2009
2008
Efficient Implementation of WiMAX Physical Layer on Multi-core Architectures with Dynamically Reconfigurable Processors.
Scalable Comput. Pract. Exp., 2008
Exploiting loop-level parallelism on multi-core architectures for the wimax physical layer.
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008
MRPSIM: A TLM based simulation tool for MPSOCS targeting dynamically reconfigurable processors.
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008
Multi-core Architectures with Dynamically Reconfigurable Array Processors for the WiMAX Physical Layer.
Proceedings of the IEEE Symposium on Application Specific Processors, 2008
Efficient Implementation of Wireless Applications on Multi-core Platforms Based on Dynamically Reconfigurable Processors.
Proceedings of the Second International Conference on Complex, 2008
2007
The Design of Multitasking Based Applications on Reconfigurable Instruction Cell Bsed Architectures.
Proceedings of the FPL 2007, 2007
2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005
Multiplier-less based parallel-pipelined FFT architectures for wireless communication applications.
Proceedings of the 2005 IEEE International Conference on Acoustics, 2005
The development of high performance FFT IP cores through hybrid low power algorithmic methodology.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005