Wei Ding

Affiliations:
  • Qualcomm Innovation Center Inc., San Diego, CA, USA
  • Pennsylvania State University, USA (PhD 2014)


According to our database1, Wei Ding authored at least 24 papers between 2011 and 2017.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2017
Cache Hierarchy-Aware Query Mapping on Emerging Multicore Architectures.
IEEE Trans. Computers, 2017

DEMM: A Dynamic Energy-Saving Mechanism for Multicore Memories.
Proceedings of the 25th IEEE International Symposium on Modeling, 2017

2015
Optimizing off-chip accesses in multicores.
Proceedings of the 36th ACM SIGPLAN Conference on Programming Language Design and Implementation, 2015

Network footprint reduction through data access and computation placement in NoC-based manycores.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Reactive tiling.
Proceedings of the 13th Annual IEEE/ACM International Symposium on Code Generation and Optimization, 2015

2014
CApRI: CAche-conscious data reordering for irregular codes.
Proceedings of the ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer Systems, 2014

Compiler Support for Optimizing Memory Bank-Level Parallelism.
Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014

Quantifying and Optimizing the Impact of Victim Cache Line Selection in Manycore Systems.
Proceedings of the IEEE 22nd International Symposium on Modelling, 2014

A cache topology-aware multi-query scheduler for multicore architectures.
Proceedings of the 2014 IEEE International Symposium on Workload Characterization, 2014

Trading cache hit rate for memory performance.
Proceedings of the International Conference on Parallel Architectures and Compilation, 2014

2013
Compiler-directed file layout optimization for hierarchical storage systems.
Sci. Program., 2013

Data layout optimization for GPGPU architectures.
Proceedings of the ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2013

Locality-aware mapping and scheduling for multicores.
Proceedings of the 2013 IEEE/ACM International Symposium on Code Generation and Optimization, 2013

Reshaping cache misses to improve row-buffer locality in multicore systems.
Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, 2013

2012
A compiler framework for extracting superword level parallelism.
Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation, 2012

Improving last level cache locality by integrating loop and data transformations.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

A hybrid NoC design for cache coherence optimization for chip multiprocessors.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Off-chip access localization for NoC-based multicores.
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2012

2011
A data layout optimization framework for NUCA-based multicores.
Proceedings of the 44rd Annual IEEE/ACM International Symposium on Microarchitecture, 2011

Exploring heterogeneous NoC design space.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Optimizing data locality using array tiling.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

On-chip cache hierarchy-aware tile scheduling for multicore machines.
Proceedings of the CGO 2011, 2011

Optimizing Data Layouts for Parallel Computation on Multicores.
Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011

Compiler Directed Data Locality Optimization for Multicore Architectures.
Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011


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