Wei-Cheng Lien

Proceedings of the 2016 IEEE International Test Conference, 2016

2014

Capture-Power-Safe Test Pattern Determination for At-Speed Scan-Based Testing.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Efficient LFSR Reseeding Based on Internal-Response Feedback.

[BibT_eX]

[DOI]

J. Electron. Test., 2014

An efficient diagnosis method to deal with multiple fault-pairs simultaneously using a single circuit model.

[BibT_eX]

[DOI]

Cheng-Hung Wu

Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

Output selection for test response compaction based on multiple counters.

[BibT_eX]

[DOI]

Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014

Output-bit selection with X-avoidance using multiple counters for test-response compaction.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE European Test Symposium, 2014

Integrated 4H-silicon carbide diode bridge rectifier for high temperature (773 K) environment.

[BibT_eX]

[DOI]

Proceedings of the 44th European Solid State Device Research Conference, 2014

2013

Counter-Based Output Selection for Test Response Compaction.

[BibT_eX]

[DOI]

Yu-Hua Wu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

An Efficient On-Chip Test Generation Scheme Based on Programmable and Multiple Twisted-Ring Counters.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

A New LFSR Reseeding Scheme via Internal Response Feedback.

[BibT_eX]

[DOI]

Proceedings of the 22nd Asian Test Symposium, 2013

2012

Routing-efficient implementation of an internal-response-based BIST architecture.

[BibT_eX]

[DOI]

Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

Accumulator-based output selection for test response compaction.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Extreme temperature 4H-SiC metal-semiconductor-metal ultraviolet photodetectors.

[BibT_eX]

[DOI]

Proceedings of the 2012 European Solid-State Device Research Conference, 2012

A Test-Per-Clock LFSR Reseeding Algorithm for Concurrent Reduction on Test Sequence Length and Test Data Volume.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE Asian Test Symposium, 2012

2011

Test Response Compaction via Output Bit Selection.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

2010

A Complete Logic BIST Technology with No Storage Requirement.

[BibT_eX]

[DOI]