Wei Chen

According to our database, Wei Chen authored at least 4 papers between 2007 and 2018.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2018

SkyLake-SP: A 14nm 28-Core xeon® processor.

Simon M. Tam, Harry Muljono, Min Huang, Sitaraman Iyer, Kalapi Royneogi, Nagmohan Satti, Rizwan Qureshi, Wei Chen, Tom Wang, Hubert Hsieh, Sujal Vora, Eddie Wang

Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2015

A 22 nm 15-Core Enterprise Xeon® Processor Family.

Stefan Rusu, Harry Muljono, David Ayers, Simon M. Tam, Wei Chen, Aaron Martin, Shenggao Li, Sujal Vora, Raj Varada, Eddie Wang

IEEE J. Solid State Circuits, 2015

2014

5.4 Ivytown: A 22nm 15-core enterprise Xeon® processor family.

Stefan Rusu, Harry Muljono, David Ayers, Simon M. Tam, Wei Chen, Aaron Martin, Shenggao Li, Sujal Vora, Raj Varada, Eddie Wang

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2007

The 65-nm 16-MB Shared On-Die L3 Cache for the Dual-Core Intel Xeon Processor 7100 Series.

Jonathan Chang, Ming Huang, Jonathan Shoemaker, John Benoit, Szu-Liang Chen, Wei Chen, Siufu Chiu, Raghuraman Ganesan, Gloria Leong, Venkata Lukka, Stefan Rusu, Durgesh Srivastava

IEEE J. Solid State Circuits, 2007