Wei-Bin Yang

Orcid: 0000-0003-4185-0776

According to our database¹, Wei-Bin Yang authored at least 38 papers between 1999 and 2024.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of four.

Timeline

Legend:

Book

In proceedings

Article

PhD thesis

Dataset

Other

Links

On csauthors.net:

Bibliography

2024

Texture Classification Network Integrating Adaptive Wavelet Transform.

[BibT_eX]

[DOI]

CoRR, 2024

A Hierarchical Tree-Structured Control Digital Low Drop-out Regulator with Status-Dumping Mechanism.

[BibT_eX]

[DOI]

Proceedings of the 21st International SoC Design Conference, 2024

A Programmable DLL-based Delay Chain.

[BibT_eX]

[DOI]

Proceedings of the 21st International SoC Design Conference, 2024

2022

A Programmable Multiple Frequencies Clock Generator With Process and Temperature Compensation Circuit for System on Chip Design.

[BibT_eX]

[DOI]

Wei-Bin Yang

Kuo-Ning Chang

Lu-Chun Yeh

IEEE Syst. J., 2022

ThreshNet: An Efficient DenseNet Using Threshold Mechanism to Reduce Connections.

[BibT_eX]

[DOI]

IEEE Access, 2022

2021

Instrumentation of Twin-MCMs based mutual-test.

[BibT_eX]

[DOI]

Microelectron. J., 2021

Asynchronous Digital Low-Dropout Regulator With Dual Adjustment Mode in Ultra-Low Voltage Input.

[BibT_eX]

[DOI]

IEEE Access, 2021

Asynchronous Domino Binary search Digital LDO.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Intelligent Signal Processing and Communication Systems, 2021

2017

A Selectable Discrete-Voltage Output and Fast-Settling Low-Dropout Regulator Using Half Digitally-Assistant Voltage Accelerator.

[BibT_eX]

[DOI]

Wei-Bin Yang

Ming-Hao Hong

Jsung Mo Shen

J. Signal Process. Syst., 2017

Design of Fast-Locked Digitally Controlled Low-Dropout Regulator for Ultra-low Voltage Input.

[BibT_eX]

[DOI]

Wei-Bin Yang

Yu-Yao Lin

Yu-Lung Lo

Circuits Syst. Signal Process., 2017

2016

A 25 MHz crystal less clock generator with background calibration against process and temperature variation.

[BibT_eX]

[DOI]

Wei-Bin Yang

Ming-Hao Hong

Comput. Electr. Eng., 2016

2015

Analysis and design considerations of static CMOS logics under process, voltage and temperature variation in UMC 0.18µm CMOS process.

[BibT_eX]

[DOI]

Proceedings of the 2015 International Symposium on Intelligent Signal Processing and Communication Systems, 2015

2013

A multiple frequency clock generator using wide operation frequency range phase interpolator.

[BibT_eX]

[DOI]

Microelectron. J., 2013

A GHz full-division-range programmable divider with output duty-cycle improved.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013

2012

A 300 mV 10 MHz 4 kb 10T subthreshold SRAM for ultralow-power application.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Intelligent Signal Processing and Communications Systems, 2012

2011

A 0.5 V 320 MHz 8 bit×8 bit pipelined multiplier in 130 nm CMOS process.

[BibT_eX]

[DOI]

Wei-Bin Yang

Chao-Cheng Liao

Yung-Chih Liang

Microelectron. J., 2011

A synthesizable pseudo fractional-N clock generator with improved duty cycle output.

[BibT_eX]

[DOI]

Wei-Bin Yang

Chang-Yo Hsieh

Microelectron. J., 2011

A new temperature independent current controlled oscillator.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Intelligent Signal Processing and Communications Systems, 2011

2010

A Pseudo Fractional-<i>N</i> Clock Generator with 50% Duty Cycle Output.

[BibT_eX]

[DOI]

Wei-Bin Yang

Yu-Lung Lo

Ting-Sheng Chao

IEICE Trans. Electron., 2010

2009

Designing an Ultralow-Voltage Phase-Locked Loop Using a Bulk-Driven Technique.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2009

High-Speed and Ultra-Low-Voltage Divide-by-4/5 Counter for Frequency Synthesizer.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2009

Designing ultra-low voltage PLL Using a bulk-driven technique.

[BibT_eX]

[DOI]

Proceedings of the 35th European Solid-State Circuits Conference, 2009

0.5V 160-MHz 260uW all digital phase-locked loop.

[BibT_eX]

[DOI]

Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2009

2008

A Spread-Spectrum Clock Generator Using Fractional PLL Controlled Delta-Sigma Modulator for Serial-ATA III.

[BibT_eX]

[DOI]

Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008

2007

New Power Gating Structure with Low Voltage Fluctuations by Bulk Controller in Transition Mode.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

A 100 MHz-1 GHz Adaptive Bandwidth PLL Using TDC Technique.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Conference on Electronics, 2007

2006

The new improved pseudo fractional-N clock generator with 50% duty cycle.

[BibT_eX]

[DOI]

Shu-Chang Kuo

Tzu-Chien Hung

Wei-Bin Yang

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A New Dynamic Floating Input D Flip-Flop (DFIDFF) for High Speed and Ultra Low Voltage Divided-by 4/5 Prescaler.

[BibT_eX]

[DOI]

Ting-Sheng Jau

Wei-Bin Yang

Yu-Lung Lo

Proceedings of the 13th IEEE International Conference on Electronics, 2006

A Variable Duty Cycle with High-Resolution Synchronous Mirror Delay.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on Electronics, 2006

Analysis and Design of High Performance, Low Power Multiple Ports Register Files.

[BibT_eX]

[DOI]

Ting-Sheng Jau

Wei-Bin Yang

Chung-Yu Chang

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005

A 2GHz fully differential DLL-based frequency multiplier for high speed serial link circuit.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

The new approach of programmable pseudo fractional-N clock generator for GHz operation with 50% duty cycle.

[BibT_eX]

[DOI]

Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005

2004

A dual-slope phase frequency detector and charge pump architecture to achieve fast locking of phased-locked loop.

[BibT_eX]

[DOI]

Kuo-Hsing Cheng

Wei-Bin Yang

Shu-Chang Kuo

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003

A dual-slope phase frequency detector and charge pump architecture to achieve fast locking of phase-locked loop.

[BibT_eX]

[DOI]

Kuo-Hsing Cheng

Wei-Bin Yang

Cheng-Ming Ying

IEEE Trans. Circuits Syst. II Express Briefs, 2003

2001

A low-power high driving ability voltage control oscillator used in PLL.

[BibT_eX]

[DOI]

Kuo-Hsing Cheng

Wei-Bin Yang

Chun-Fu Chung

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

A difference detector PFD for low jitter PLL.

[BibT_eX]

[DOI]

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

A CMOS low power voltage controlled oscillator with split-path controller.

[BibT_eX]

[DOI]

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

1999

The suggestion for CFS CMOS buffer.

[BibT_eX]

[DOI]

Kuo-Hsing Cheng

Wei-Bin Yang

Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

Wei-Bin Yang

Timeline

Legend:

Links

On csauthors.net:

Bibliography

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