Wayne P. Burleson
Orcid: 0000-0002-7068-4351Affiliations:
- University of Massachusetts Amherst, Department of Electrical and Computer Engineering, MA, USA
According to our database1,
Wayne P. Burleson
authored at least 191 papers
between 1989 and 2023.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 2011, "For contributions to integrated circuit design and signal processing".
Timeline
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Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
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on orcid.org
On csauthors.net:
Bibliography
2023
ACM Trans. Reconfigurable Technol. Syst., March, 2023
Survey of Security Issues in Memristor-based Machine Learning Accelerators for RF Analysis.
CoRR, 2023
2022
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2022
J. Cryptogr. Eng., 2022
2021
IEEE Micro, 2021
Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021
2020
Cybersecurity of Hospitals: discussing the challenges and working towards mitigating the risks.
BMC Medical Informatics Decis. Mak., 2020
Understanding and Comparing the Capabilities of On-Chip Voltage Sensors against Remote Power Attacks on FPGAs.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020
Proceedings of the 4th ACM Workshop on Attacks and Solutions in Hardware Security Workshop, 2020
2019
Guest Editorial Special Section on Security Challenges and Solutions With Emerging Computing Technologies.
IEEE Trans. Very Large Scale Integr. Syst., 2019
PVTMC: An All-Digital Sub-Picosecond Timing Measurement Circuit Based on Process Variations.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019
Combining Clock and Voltage Noise Countermeasures Against Power Side-Channel Analysis.
Proceedings of the 30th IEEE International Conference on Application-specific Systems, 2019
2018
Enhancing Power, Performance, and Energy Efficiency in Chip Multiprocessors Exploiting Inverse Thermal Dependence.
IEEE Trans. Very Large Scale Integr. Syst., 2018
IACR Cryptol. ePrint Arch., 2018
Implications of Integrated CPU-GPU Processors on Thermal and Power Management Techniques.
CoRR, 2018
2017
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017
An asynchronous NoC router in a 14nm FinFET library: Comparison to an industrial synchronous counterpart.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
2016
ACM Trans. Embed. Comput. Syst., 2016
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016
Workload-Aware Power Gating Design and Run-Time Management for Massively Parallel GPGPUs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016
Invited - Who is the major threat to tomorrow's security?: you, the hardware designer.
Proceedings of the 53rd Annual Design Automation Conference, 2016
2015
Entropy and Energy Bounds for Metastability Based TRNG with Lightweight Post-Processing.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
IACR Cryptol. ePrint Arch., 2015
PLayPUF: Programmable Logically Erasable PUFs for Forward and Backward Secure Key Management.
IACR Cryptol. ePrint Arch., 2015
Proceedings of the 2015 IEEE Symposium on Security and Privacy, 2015
Side-Channel Assisted Modeling Attacks on Feed-Forward Arbiter PUFs Using Silicon Data.
Proceedings of the Radio Frequency Identification. Security and Privacy Issues, 2015
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015
2014
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014
IACR Cryptol. ePrint Arch., 2014
Proceedings of the 27th IEEE International System-on-Chip Conference, 2014
Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014
Keynote talk I: Security and privacy in implantable medical devices: An ongoing concern.
Proceedings of the Twelfth ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2014
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014
Proceedings of the 2014 IEEE International Symposium on Hardware-Oriented Security and Trust, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Special session: How secure are PUFs really? On the reach and limits of recent PUF attacks.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2014, 2014
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2014
2013
Timing Uncertainty in 3-D Clock Trees Due to Process Variations and Power Supply Noise.
IEEE Trans. Very Large Scale Integr. Syst., 2013
IEEE Trans. Inf. Forensics Secur., 2013
IACR Cryptol. ePrint Arch., 2013
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013
Proceedings of the Privacy Enhancing Technologies - 13th International Symposium, 2013
Litho-aware and low power design of a secure current-based physically unclonable function.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013
Proceedings of the 2013 IEEE International Symposium on Hardware-Oriented Security and Trust, 2013
Run-time probabilistic detection of miscalibrated thermal sensors in many-core systems.
Proceedings of the Design, Automation and Test in Europe, 2013
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2013, 2013
2012
Compact Expressions for Supply Noise Induced Period Jitter of Global Binary Clock Trees.
IEEE Trans. Very Large Scale Integr. Syst., 2012
Design and Validation of Arbiter-Based PUFs for Sub-45-nm Low-Power Security Applications.
IEEE Trans. Inf. Forensics Secur., 2012
IEEE Trans. Inf. Forensics Secur., 2012
An architecture-independent instruction shuffler to protect against side-channel attacks.
ACM Trans. Archit. Code Optim., 2012
TARDIS: Time and Remanence Decay in SRAM to Implement Secure Protocols on Embedded Devices without Clocks.
Proceedings of the 21th USENIX Security Symposium, Bellevue, WA, USA, August 8-10, 2012, 2012
DRV-Fingerprinting: Using Data Retention Voltage of SRAM Cells for Chip Identification.
Proceedings of the Radio Frequency Identification. Security and Privacy Issues, 2012
Privacy Preserving Payments on Computational RFID Devices with Application in Intelligent Transportation Systems.
Proceedings of the Radio Frequency Identification. Security and Privacy Issues, 2012
Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012
The combined effect of process variations and power supply noise on clock skew and jitter.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012
Robust metastability-based TRNG design in nanometer CMOS with sub-vdd pre-charge and hybrid self-calibration.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
2011
IEEE Trans. Very Large Scale Integr. Syst., 2011
Temperature Effects on Practical Energy Optimization of Sub-Threshold Circuits in Deep Nanometer Technologies.
J. Low Power Electron., 2011
A 12.4μm<sup>2</sup> 133.4μW 4.56mV/°C resolution digital on-chip thermal sensing circuit in 45nm CMOS utilizing sub-threshold operation.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011
Proceedings of the IEEE 29th International Conference on Computer Design, 2011
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011
A 45.6μ<sup>2</sup> 13.4μw 7.1v/v resolution sub-threshold based digital process-sensing circuit in 45nm CMOS.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011
2010
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010
Analysis and mitigation of NBTI-impact on PVT variability in repeated global interconnect performance.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010
Proceedings of the Design, Automation and Test in Europe, 2010
2009
IEEE Trans. Computers, 2009
Microprocess. Microsystems, 2009
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009
On temperature planarization effect of copper dummy fills in deep nanometer technology.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009
Low-power, process-variation tolerant on-chip thermal monitoring using track and hold based thermal sensors.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009
Proceedings of the Design, Automation and Test in Europe, 2009
Proceedings of the 46th Design Automation Conference, 2009
Proceedings of the Cryptographic Hardware and Embedded Systems, 2009
2008
Reconfigurable Hardware for High-Security/ High-Performance Embedded Systems: The SAFES Perspective.
IEEE Trans. Very Large Scale Integr. Syst., 2008
Temperature measurement in Content Addressable Memory cells using bias-controlled VCO.
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Collaborative sensing of on-chip wire temperatures using interconnect based ring oscillators.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008
2007
IEEE Trans. Very Large Scale Integr. Syst., 2007
Proceedings of the IFIP VLSI-SoC 2007, 2007
Low latency Solution for Confidentiality and Integrity Checking in Embedded Systems with Off-Chip Memory.
Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2007
Proceedings of the First International Symposium on Networks-on-Chips, 2007
Distributed Collaborative Adaptive Sensing: A Unifying Theme for a Junior Level Embedded Systems Course.
Proceedings of the IEEE International Conference on Microelectronic Systems Education, 2007
High-efficiency protection solution for off-chip memory in embedded systems.
Proceedings of the 2007 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2007
An Energy-efficient Multi-bit Quaternary Current-mode Signaling for On-chip Interconnects.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007
2006
Int. J. Embed. Syst., 2006
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006
Proceedings of the 39th Hawaii International International Conference on Systems Science (HICSS-39 2006), 2006
2005
IEEE Trans. Very Large Scale Integr. Syst., 2005
IEEE Trans. Computers, 2005
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005
Proceedings of the Embedded Computer Systems: Architectures, 2005
Digital Systems Design with ASIC and FPGA: A Novel Course Using CD/DVD and On-Line Formats.
Proceedings of the 2005 International Conference on Microelectronics Systems Education, 2005
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005
Proceedings of the 2005 International Symposium on System-on-Chip, 2005
Robust Multi-Level Current-Mode On-Chip Interconnect Signaling in the Presence of Process Variations.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005
Proceedings of the 31st European Solid-State Circuits Conference, 2005
2004
J. VLSI Signal Process., 2004
Trading off transient fault tolerance and power consumption in deep submicron (DSM) VLSI circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2004
IEEE Trans. Very Large Scale Integr. Syst., 2004
NoCIC: a spice-based interconnect planning tool emphasizing aggressive on-chip interconnect circuit methods.
Proceedings of the Sixth International Workshop on System-Level Interconnect Prediction (SLIP 2004), 2004
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004
Synchro-Tokens: Eliminating Nondeterminism to Enable Chip-Level Test of Globally-Asynchronous Locally-Synchronous SoC?s.
Proceedings of the 2004 Design, 2004
2003
Proceedings of the 2003 International Conference on Microelectronics Systems Education, 2003
Proceedings of the 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), 2003
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003
Adaptive system on a chip (ASOC): a backbone for power-aware signal processing cores.
Proceedings of the 2003 International Conference on Image Processing, 2003
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003
Proceedings of the ESSCIRC 2003, 2003
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003
2002
Boosters for driving long onchip interconnects - design issues, interconnect synthesis, and comparison with repeaters.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002
Proceedings of the Power-Aware Computer Systems, Second International Workshop, 2002
Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2002
2001
J. VLSI Signal Process., 2001
J. VLSI Signal Process., 2001
Boosters for driving long on-chip interconnects: design issues, interconnect synthesis and comparison with repeaters.
Proceedings of the 2001 International Symposium on Physical Design, 2001
Dynamically parameterized algorithms and architectures to exploit signal variations for improved performance and reduced power.
Proceedings of the IEEE International Conference on Acoustics, 2001
Dynamically Parameterized Architectures for Power-Aware Video Coding: Motion Estimation and DCT.
Proceedings of the 2nd International Workshop on Digital and Computational Video (DCV 2001), 2001
2000
Proceedings of the Power-Aware Computer Systems, First International Workshop, 2000
Repeater insertion in deep sub-micron CMOS: ramp-based analytical model and placement sensitivity analysis.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Low power digital design in FPGAs: a study of pipeline architectures implemented in a FPGA using a low supply voltage to reduce power consumption.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Proceedings of the 2000 IEEE International Conference on Multimedia and Expo, 2000
Low power digital design in FPGAs (poster abstract): a study of pipeline architectures implemented in a FPGA using a low supply voltage to reduce power consumption.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2000
1999
IEEE Trans. Very Large Scale Integr. Syst., 1999
Proceedings of the Field-Programmable Logic and Applications, 9th International Workshop, 1999
Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays, 1999
1998
Performance optimization of wireless local area networks through VLSI data compression.
Wirel. Networks, 1998
J. VLSI Signal Process., 1998
IEEE Trans. Very Large Scale Integr. Syst., 1998
IEEE Trans. Very Large Scale Integr. Syst., 1998
Proceedings of the 1998 IEEE International Conference on Acoustics, 1998
1997
IEEE Trans. Very Large Scale Integr. Syst., 1997
IEEE Trans. Very Large Scale Integr. Syst., 1997
Proceedings of the 1997 IEEE International Conference on Acoustics, 1997
1996
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996
1995
IEEE Trans. Very Large Scale Integr. Syst., 1995
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995
Proceedings of the 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), 1995
Proceedings of the 32st Conference on Design Automation, 1995
1994
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994
Using Regular Array Methods for DSP Module Synthesis.
Proceedings of the 27th Annual Hawaii International Conference on System Sciences (HICSS-27), 1994
Proceedings of the International Conference on Application Specific Array Processors, 1994
1993
Proceedings of the Real-Time Systems Symposium. Raleigh-Durham, NC, USA, December 1993, 1993
Rank-order Filtering Algorithms: A Comparison of VLSI Implementations.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993
Proceedings of the International Conference on Application-Specific Array Processors, 1993
Node merging: A transformation on bit-level dependence graphs for efficient VLSI array design.
Proceedings of the International Conference on Application-Specific Array Processors, 1993
Proceedings of the International Conference on Application-Specific Array Processors, 1993
1992
Proceedings of the Application Specific Array Processors, 1992
1991
Input/Output Design for VLSI Array Architectures.
Proceedings of the VLSI 91, 1991
Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991
Proceedings of the 1991 International Conference on Acoustics, 1991
1989
IEEE J. Solid State Circuits, April, 1989