Wataru Uesugi
According to our database1,
Wataru Uesugi
authored at least 5 papers
between 2014 and 2017.
Collaborative distances:
Collaborative distances:
Timeline
2014
2015
2016
2017
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Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2017
Embedded Memory and ARM Cortex-M0 Core Using 60-nm C-Axis Aligned Crystalline Indium-Gallium-Zinc Oxide FET Integrated With 65-nm Si CMOS.
IEEE J. Solid State Circuits, 2017
2016
Embedded memory and ARM Cortex-M0 core using 60-nm C-axis aligned crystalline indium-gallium-zinc oxide FET integrated with 65-nm Si CMOS.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016
2014
IEEE Micro, 2014
A 32-bit CPU with zero standby power and 1.5-clock sleep/2.5-clock wake-up achieved by utilizing a 180-nm C-axis aligned crystalline In-Ga-Zn oxide transistor.
Proceedings of the Symposium on VLSI Circuits, 2014
Embedded SRAM and Cortex-M0 core with backup circuits using a 60-nm crystalline oxide semiconductor for power gating.
Proceedings of the 2014 IEEE Symposium on Low-Power and High-Speed Chips, 2014