Wangqi Qiu

According to our database, Wangqi Qiu authored at least 16 papers between 2003 and 2016.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2016

Macro Model of Advanced Devices for Parasitic Extraction.

Yuhan Zhou, Yong Zhang, Vivek Sarin, Wangqi Qiu, Weiping Shi

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

2007

Fault simulation and test generation for small delay faults.

Wangqi Qiu

PhD thesis, 2007

2006

Comparison of Delay Tests on Silicon.

Wangqi Qiu, D. M. H. Walker, Neil Simpson, Divya Reddy, Anthony Moore

Proceedings of the 2006 IEEE International Test Conference, 2006

2005

Longest-path selection for delay test under process variation.

Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, Weiping Shi

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Static Compaction of Delay Tests Considering Power Supply Noise.

Jing Wang, Xiang Lu, Wangqi Qiu, Ziding Yue, Steve Fancler, Weiping Shi, D. M. H. Walker

Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

A vector-based approach for power supply noise analysis in test compaction.

Jing Wang, Ziding Yue, Xiang Lu, Wangqi Qiu, Weiping Shi, D. M. H. Walker

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

2004

A Statistical Fault Coverage Metric for Realistic Path Delay Faults.

Wangqi Qiu, Xiang Lu, Jing Wang, Zhuo Li, D. M. H. Walker, Weiping Shi

Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

Minimum moment Steiner trees.

Wangqi Qiu, Weiping Shi

Proceedings of the Fifteenth Annual ACM-SIAM Symposium on Discrete Algorithms, 2004

A Circuit Level Fault Model for Resistive Shorts of MOS Gate Oxide.

Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, Weiping Shi

Proceedings of the Fifth International Workshop on Microprocessor Test and Verification (MTV 2004), 2004

K Longest Paths Per Gate (KLPG) Test Generation for Scan-Based Sequential Circuits.

Wangqi Qiu, Jing Wang, D. M. H. Walker, Divya Reddy, Zhuo Li, Weiping Shi, Hari Balachandran

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

PARADE: PARAmetric Delay Evaluation under Process Variation.

Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, Weiping Shi

Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

2003

A circuit level fault model for resistive bridges.

Zhuo Li, Xiang Lu, Wangqi Qiu, Weiping Shi, D. M. H. Walker

ACM Trans. Design Autom. Electr. Syst., 2003

A Circuit Level Fault Model for Resistive Opens and Bridges.

Zhuo Li, Xiang Lu, Wangqi Qiu, Weiping Shi, D. M. H. Walker

Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

Testing the Path Delay Faults of ISCAS85 Circuit c6288.

Wangqi Qiu, D. M. H. Walker

Proceedings of the Fourth International Workshop on Microprocessor Test and Verification, 2003

An Efficient Algorithm for Finding the K Longest Testable Paths Through Each Gate in a Combinational Circuit.

Wangqi Qiu, D. M. H. Walker

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

CodSim -- A Combined Delay Fault Simulator.

Wangqi Qiu, Xiang Lu, Zhuo Li, D. M. H. Walker, Weiping Shi

Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003