Wang Kang

Orcid: 0000-0002-3169-6034

Affiliations:
  • Fert Beijing Institute, China
  • Beihang University, BDBC, School of Integrated Circuit Science and Engineering, School of Microelectronics, China
  • University of Paris-Sud, IEF, France (PhD 2015)


According to our database1, Wang Kang authored at least 88 papers between 2012 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Online presence:

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Bibliography

2024
CIM²PQ: An Arraywise and Hardware-Friendly Mixed Precision Quantization Method for Analog Computing-In-Memory.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., July, 2024

Toward Write Optimization for Skyrmion Racetrack Memory by Skyrmion Repermutation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., June, 2024

An End-to-End In-Memory Computing System Based on a 40-nm eFlash-Based IMC SoC: Circuits, Toolchains, and Systems Co-Design Framework.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., June, 2024

Toward Energy-efficient STT-MRAM-based Near Memory Computing Architecture for Embedded Systems.
ACM Trans. Embed. Comput. Syst., May, 2024

CiTST-AdderNets: Computing in Toggle Spin Torques MRAM for Energy-Efficient AdderNets.
IEEE Trans. Circuits Syst. I Regul. Pap., March, 2024

CIMQ: A Hardware-Efficient Quantization Framework for Computing-In-Memory-Based Neural Network Accelerators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., January, 2024

MixMixQ: Quantization with Mixed Bit-Sparsity and Mixed Bit-Width for CIM Accelerators.
Proceedings of the Great Lakes Symposium on VLSI 2024, 2024

Series-Parallel Hybrid SOT-MRAM Computing-in-Memory Macro with Multi-Method Modulation for High Area and Energy Efficiency.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

2023
Partial Sum Quantization for Computing-In-Memory-Based Neural Network Accelerator.
IEEE Trans. Circuits Syst. II Express Briefs, August, 2023

Experimental Demonstration of STT-MRAM-based Nonvolatile Instantly On/Off System for IoT Applications: Case Studies.
ACM Trans. Embed. Comput. Syst., March, 2023

A Reconfigurable Spatial Architecture for Energy-Efficient Inception Neural Networks.
IEEE J. Emerg. Sel. Topics Circuits Syst., March, 2023

Granularity-Driven Management for Reliable and Efficient Skyrmion Racetrack Memories.
IEEE Trans. Emerg. Top. Comput., 2023

Differentiable Multi-Fidelity Fusion: Efficient Learning of Physics Simulations with Neural Architecture Search and Transfer Learning.
CoRR, 2023

Roadmap for Unconventional Computing with Nanotechnology.
CoRR, 2023

ES-MPQ: Evolutionary Search Enabled Mixed Precision Quantization Framework for Computing-in-Memory.
Proceedings of the 12th Non-Volatile Memory Systems and Applications Symposium, 2023

An In-Memory-Computing STT-MRAM Macro with Analog ReLU and Pooling Layers for Ultra-High Efficient Neural Network.
Proceedings of the 12th Non-Volatile Memory Systems and Applications Symposium, 2023

Exploring Bit-Level Sparsity for Partial Sum Quantization in Computing-In-Memory Accelerator.
Proceedings of the 12th Non-Volatile Memory Systems and Applications Symposium, 2023

OPT: Optimal Proposal Transfer for Efficient Yield Optimization for Analog and SRAM Circuits.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

Hierarchical Non-Structured Pruning for Computing-In-Memory Accelerators with Reduced ADC Resolution Requirement.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Skyrmion Vault: Maximizing Skyrmion Lifespan for Enabling Low-Power Skyrmion Racetrack Memory.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

Searching Tiny Neural Networks for Deployment on Embedded FPGA.
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023

2022
SpinCIM: spin orbit torque memory for ternary neural networks based on the computing-in-memory architecture.
CCF Trans. High Perform. Comput., December, 2022

A Mini Tutorial of Processing in Memory: From Principles, Devices to Prototypes.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

A Spintronic In-Memory Computing Network for Efficient Hamming Codec Implementation.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

HD-CIM: Hybrid-Device Computing-In-Memory Structure Based on MRAM and SRAM to Reduce Weight Loading Energy of Neural Networks.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

CP-SRAM: charge-pulsation SRAM marco for ultra-high energy-efficiency computing-in-memory.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

Efficient bayesian yield analysis and optimization with active learning.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021
Forecasting the outcome of spintronic experiments with Neural Ordinary Differential Equations.
CoRR, 2021

HSC: A Hybrid Spin/CMOS Logic Based In-Memory Engine with Area-Efficient Mapping Strategy.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Spin-Orbit Torque Nonvolatile Flip-Flop Designs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

A 40nm 33.6Tops/W 8T-SRAM Computing-in-Memory Macro with DAC-less Spike-Pulse-Truncation Input and ADC-less Charge-Reservoir-Integrate-Counter Output.
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021

SpinLiM: Spin Orbit Torque Memory for Ternary Neural Networks Based on the Logic-in-Memory Architecture.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Tiny neural network search and implementation for embedded FPGA: a software-hardware co-design approach.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021

2020
Shift-Limited Sort: Optimizing Sorting Performance on Skyrmion Memory-Based Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

A Comparative Cross-layer Study on Racetrack Memories: Domain Wall vs Skyrmion.
ACM J. Emerg. Technol. Comput. Syst., 2020

Deep Neural Network accelerator with Spintronic Memory.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

High-Density, Low-Power Voltage-Control Spin Orbit Torque Memory with Synchronous Two-Step Write and Symmetric Read Techniques.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
An STT-MRAM Based in Memory Architecture for Low Power Integral Computing.
IEEE Trans. Computers, 2019

Low-Power (1T1N) Skyrmionic Synapses for Spiking Neuromorphic Systems.
IEEE Access, 2019

Spintronic Memories: From Memory to Computing-in-Memory.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2019

Exploiting Near-Memory Processing Architectures for Bayesian Neural Networks Acceleration.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

SR-WTA: Skyrmion Racing Winner-Takes-All Module for Spiking Neural Computing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Magnetic Skyrmion-Based Neural Recording System Design for Brain Machine Interface.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Voltage-Controlled Magnetoelectric Memory Bit-cell Design With Assisted Body-bias in FD-SOI.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

ZUMA: Enabling Direct Insertion/Deletion Operations with Emerging Skyrmion Racetrack Memory.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
A Full-Sensing-Margin Dual-Reference Sensing Scheme for Deeply-Scaled STT-RAM.
IEEE Access, 2018

Multi-bit nonvolatile flip-flop based on NAND-like spin transfer torque MRAM.
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018

A Comparative Study on Racetrack Memories: Domain Wall vs. Skyrmion.
Proceedings of the IEEE 7th Non-Volatile Memory Systems and Applications Symposium, 2018

A Novel Cross-point MRAM with Diode Selector Capable of High-Density, High-Speed, and Low-Power In-Memory Computation.
Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, 2018

A Robust Dual Reference Computing-in-Memory Implementation and Design Space Exploration Within STT-MRAM.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Emerging Neuromorphic Computing Paradigms Exploring Magnetic Skyrmions.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

MRAM-on-FDSOI Integration: A Bit-Cell Perspective.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Progresses and challenges of spin orbit torque driven magnetization switching and application (Invited).
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Design and Data Management for Magnetic Racetrack Memory.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Enabling Resilient Voltage-Controlled MeRAM Using Write Assist Techniques.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Magnetic skyrmions for future potential memory and logic applications: Alternative information carriers.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Process variation aware data management for magnetic skyrmions racetrack memory.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

High-Density and Fast-Configuration Non-Volatile Look-Up Table Based on NAND-Like Spintronic Memory.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

2017
Dynamic Dual-Reference Sensing Scheme for Deep Submicrometer STT-MRAM.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

Pseudo-Differential Sensing Framework for STT-MRAM: A Cross-Layer Perspective.
IEEE Trans. Computers, 2017

Programmable Stateful In-Memory Computing Paradigm via a Single Resistive Device.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Advanced Low Power Spintronic Memories beyond STT-MRAM.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Energy Efficient Magnetic Tunnel Junction Based Hybrid LSI Using Multi-Threshold UTBB-FD-SOI Device.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Voltage-controlled MRAM for working memory: Perspectives and challenges.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Ultrafast spintronic integrated circuits.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

2016
Skyrmion-Electronics: An Overview and Outlook.
Proc. IEEE, 2016

Read disturbance issue and design techniques for nanoscale STT-MRAM.
J. Syst. Archit., 2016

Complementary Skyrmion Racetrack Memory with Voltage Manipulation.
CoRR, 2016

Skyrmions as Compact, Robust and Energy-Efficient Interconnects for Domain Wall (DW)-based Systems.
CoRR, 2016

Magnetic skyrmion-based synaptic devices.
CoRR, 2016

Dual reference sensing scheme with triple steady states for deeply scaled STT-MRAM.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016

A spin Hall effect-based multi-level cell for MRAM.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016

Evaluation of spin-Hall-assisted STT-MRAM for cache replacement.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016

Quantitative evaluation of reliability and performance for STT-MRAM.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

PDS: pseudo-differential sensing scheme for STT-MRAM.
Proceedings of the 53rd Annual Design Automation Conference, 2016

2015
Synchronous 8-bit Non-Volatile Full-Adder based on Spin Transfer Torque Magnetic Tunnel Junction.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Spintronics: Emerging Ultra-Low-Power Circuits and Systems beyond MOS Technology.
ACM J. Emerg. Technol. Comput. Syst., 2015

Yield and Reliability Improvement Techniques for Emerging Nonvolatile STT-MRAM.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2015

Nonvolatile radiation hardened DICE latch.
Proceedings of the 15th Non-Volatile Memory Technology Symposium, 2015

Read disturbance issue for nanoscale STT-MRAM.
Proceedings of the IEEE Non-Volatile Memory System and Applications Symposium, 2015

Channel Modeling and Reliability Enhancement Design Techniques for STT-MRAM.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

2014
Design and analysis of crossbar architecture based on complementary resistive switching non-volatile memory cells.
J. Parallel Distributed Comput., 2014

One-step majority-logic-decodable codes enable STT-MRAM for high speed working memories.
Proceedings of the IEEE Non-Volatile Memory Systems and Applications Symposium, 2014

Ferroelectric tunnel memristor-based neuromorphic network with 1T1R crossbar architecture.
Proceedings of the 2014 International Joint Conference on Neural Networks, 2014

Spintronics for low-power computing.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

An overview of spin-based integrated circuits.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
A low-cost built-in error correction circuit design for STT-MRAM reliability improvement.
Microelectron. Reliab., 2013

2012
Improving flash memory reliability with dynamic thresholds: Signal processing and coding schemes.
Proceedings of the 7th International Conference on Communications and Networking in China, 2012


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