Wan-Ting Chiang

According to our database, Wan-Ting Chiang authored at least 3 papers between 2014 and 2017.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of five.

2017

A Built-Off Self-Repair Scheme for Channel-Based 3D Memories.

Hsuan-Hung Liu, Bing-Yang Lin, Cheng-Wen Wu, Wan-Ting Chiang, Mincent Lee, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang

IEEE Trans. Computers, 2017

2016

Configurable Cubical Redundancy Schemes for Channel-Based 3-D DRAM Yield Improvement.

Bing-Yang Lin, Wan-Ting Chiang, Cheng-Wen Wu, Mincent Lee, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang

IEEE Des. Test, 2016

2014

Redundancy architectures for channel-based 3D DRAM yield improvement.

Bing-Yang Lin, Wan-Ting Chiang, Cheng-Wen Wu, Mincent Lee, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang

Proceedings of the 2014 International Test Conference, 2014