Walter M. Weber

Orcid: 0000-0001-9504-5671

According to our database1, Walter M. Weber authored at least 16 papers between 2013 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Ferroelectrically-enhanced Schottky barrier transistors for Logic-in-Memory applications.
CoRR, 2024

Three-Input Combinational Logic Gates based on Reconfigurable Si Field-Effect Transistors.
Proceedings of the Device Research Conference, 2024

Realization and characterization of HZO-based Schottky-Barrier FETs towards Logic-in-Memory applications.
Proceedings of the Device Research Conference, 2024

2023
Bias Spectroscopy of Negative Differential Resistance in Ge Nanowire Cascode Circuits.
Proceedings of the 53rd IEEE European Solid-State Device Research Conference, 2023

2022
Compact Modeling of Channel-Resistance Effects in Reconfigurable Field-Effect Transistors.
Proceedings of the 29th International Conference on Mixed Design of Integrated Circuits and System, 2022

2019
Designing Efficient Circuits Based on Runtime-Reconfigurable Field-Effect Transistors.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Eliminating Charge Sharing in Clocked Logic Gates on the Device Level Employing Transistors with Multiple Independent Inputs.
Proceedings of the 49th European Solid-State Device Research Conference, 2019


2018
A wired-AND transistor: Polarity controllable FET with multiple inputs.
Proceedings of the 76th Device Research Conference, 2018

A physical synthesis flow for early technology evaluation of silicon nanowire based reconfigurable FETs.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
Human α-thrombin detection platform using aptamers on a silicon nanowire field-effect transistor.
Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017

In-depth electrical characterization of carrier transport in ambipolar Si-NW Schottky-barrier FETs.
Proceedings of the 47th European Solid-State Device Research Conference, 2017

Exploiting transistor-level reconfiguration to optimize combinational circuits.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016
Reconfigurable nanowire transistors with multiple independent gates for efficient and programmable combinational circuits.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2014
Reconfigurable silicon nanowire devices and circuits: Opportunities and challenges.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Reconfigurable nanowire electronics - Device principles and circuit prospects.
Proceedings of the European Solid-State Device Research Conference, 2013


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