Walter Lau Neto

Orcid: 0000-0002-9349-4964

According to our database1, Walter Lau Neto authored at least 16 papers between 2016 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
Scalable Sequential Optimization Under Observability Don't Cares.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2023
FlowTune: End-to-End Automatic Logic Optimization Exploration via Domain-Specific Multiarmed Bandit.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., June, 2023

2022
A Two-Level Approximate Logic Synthesis Combining Cube Insertion and Removal.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

End-to-end Automatic Logic Optimization Exploration via Domain-specific Multi-armed Bandit.
CoRR, 2022

Improving LUT-based optimization for ASICs.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021

Invited: Getting the Most out of your Circuits with Heterogeneous Logic Synthesis.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

SLAP: A Supervised Learning Approach for Priority Cuts Technology Mapping.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

Read your Circuit: Leveraging Word Embedding to Guide Logic Optimization.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020
Exact Benchmark Circuits for Logic Synthesis.
IEEE Des. Test, 2020

A Scalable Mixed Synthesis Framework for Heterogeneous Networks.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
Improving Logic Optimization in Sequential Circuits using Majority-inverter Graphs.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

LSOracle: a Logic Synthesis Framework Driven by Artificial Intelligence: Invited Paper.
Proceedings of the International Conference on Computer-Aided Design, 2019

2018
Exact Multi-Level Benchmark Circuit Generation for Logic Synthesis Evaluation.
Proceedings of the 31st Symposium on Integrated Circuits and Systems Design, 2018

2017
Sleep convention logic isochronic fork: an analysis.
Proceedings of the 30th Symposium on Integrated Circuits and Systems Design: Chip on the Sands, 2017

2016
A standard cell characterization flow for non-standard voltage supplies.
Proceedings of the 29th Symposium on Integrated Circuits and Systems Design, 2016


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