Walter Brown

According to our database1, Walter Brown authored at least 9 papers between 2008 and 2016.

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Bibliography

2016
Formal Verification of Arithmetic Circuits by Function Extraction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

2015
Logic Debugging of Arithmetic Circuits.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Verification of arithmetic datapath designs using word-level approach - A case study.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Verification of gate-level arithmetic circuits by function extraction.
Proceedings of the 52nd Annual Design Automation Conference, 2015

2014
Function Extraction from Arithmetic Bit-Level Circuits.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

2013
Arithmetic Bit-Level Verification Using Network Flow Model.
Proceedings of the Hardware and Software: Verification and Testing, 2013

2009
Innovations for digital inclusion: Leveraging next generation networks for human development from the bottom of the pyramid.
Proceedings of the ITU Kaleidoscope 2009: Innovations for Digital Inclusions, Mar del Plata, Argentina, August 31, 2009

Towards a research framework for a human development-based "bottom of the pyramid" ICT development strategy in South Africa.
Proceedings of the 17th European Conference on Information Systems, 2009

2008
Next generation ICT policy in South Africa: Towards a human development-based ICT policy.
Proceedings of the Social Dimensions of Information And Communication Technology Policy, 2008


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