Walter Anheier

According to our database, Walter Anheier authored at least 34 papers between 1993 and 2016.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2016

Genetic-Algorithm-based Test Pattern Generation for Crosstalk Faults between On-Chip Aggressor and Victim.

Kishore K. Duganapalli, Ajoy Kumar Palit, Walter Anheier

J. Circuits Syst. Comput., 2016

2015

TPG for Crosstalk Faults between On-Chip Aggressor and Victim Using Genetic Algorithms.

Kishore K. Duganapalli, Ajoy Kumar Palit, Walter Anheier

Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015

2010

Test Pattern Generation and Compaction for Crosstalk Induced Glitches and Delay Faults.

Shehzad Hasan, Ajoy Kumar Palit, Walter Anheier

Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

Fault diagnosis of crosstalk induced glitches and delay faults.

Shehzad Hasan, Ajoy Kumar Palit, Walter Anheier

Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

Efficient Training Algorithm for Neuro-Fuzzy Network and its Application to Nonlinear Sensor Characteristic Linearization.

Ajoy Kumar Palit, Walter Anheier

Proceedings of the Intelligent Systems for Automated Learning and Adaptation: Emerging Trends and Applications, 2010

2009

Electrical Load Forecasting Using a Neural-Fuzzy Approach.

Ajoy Kumar Palit, Walter Anheier, Dobrivoje Popovic

Proceedings of the Natural Intelligence for Scheduling, Planning and Packing Problems, 2009

Timing Arc based logic analysis for false noise reduction.

Murthy Palla, Jens Bargfrede, Stephan Eggersglüß, Walter Anheier, Rolf Drechsler

Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

2008

Crosstalk fault modeling in defective pair of interconnects.

Ajoy Kumar Palit, Kishore K. Duganapalli, Walter Anheier

Integr., 2008

Adaptive Branch and Bound Using SAT to Estimate False Crosstalk.

Murthy Palla, Jens Bargfrede, Klaus Koch, Walter Anheier, Rolf Drechsler

Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

2007

XSIM: An Efficient Crosstalk Simulator for Analysis and Modeling of Signal Integrity Faults in Both Defective and Defect-free Interconnects.

Ajoy Kumar Palit, Kishore K. Duganapalli, Walter Anheier

Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

2006

Modeling of Crosstalk Fault in Defective Interconnects.

Ajoy Kumar Palit, Kishore K. Duganapalli, Walter Anheier

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

Vergleich und Optimierung von Algorithmen zur Modulo-Multiplikation auf Smartcards.

Sascha Kneip, Walter Anheier

Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2006

Reduction of Crosstalk Pessimism using Tendency Graph Approach.

Murthy Palla, Klaus Koch, Jens Bargfrede, Manfred Glesner, Walter Anheier

Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

Influence of Resistive Bridging Fault on Crosstalk Coupling Effects in On-Chip Aggressor-Victim Interconnects.

Ajoy Kumar Palit, Kishore K. Duganapalli, Walter Anheier

Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

2005

ABCD Modeling of Crosstalk Coupling Noise to Analyze the Signal Integrity Losses on the Victim Interconnect in DSM Chips.

Ajoy Kumar Palit, Volker Meyer, Walter Anheier, Jürgen Schlöffel

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

A New, Flexible and Very Accurate Crosstalk Fault Model to Analyze the Effects of Coupling Noise between the Interconnects on Signal Integrity Losses in Deep Submicron Chips.

Ajoy Kumar Palit, Lei Wu, Kishore K. Duganapalli, Walter Anheier, Jürgen Schlöffel

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2004

Modeling and Analysis of Crosstalk Coupling Effect on the Victim Interconnect Using the ABCD Network Model.

Ajoy Kumar Palit, Volker Meyer, Walter Anheier, Jürgen Schlöffel

Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004

2002

Non-robust delay test pattern enhancement.

Volker Meyer, Walter Anheier, Arne Sticht

Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

Backpropagation based training algorithm for Takagi-Sugeno type MIMO neuro-fuzzy network to forecast electrical load time series.

Ajoy Kumar Palit, Gerhard Doeding, Walter Anheier, Dobrivoje Popovic

Proceedings of the 2002 IEEE International Conference on Fuzzy Systems, 2002

2001

Integer division in residue number system.

Badreddine Rejeb, Heiko Henkelmann, Walter Anheier

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

Non-robust delay test pattern generation based on stuck-at TPG.

Volker Meyer, Walter Anheier, Arne Sticht

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

Investigations of on-line/off-line tests for sensors.

Michael Fischell, Walter Anheier

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

2000

On Random Pattern Testability of Cryptographic VLSI Cores.

A. Schubert, Walter Anheier

J. Electron. Test., 2000

1999

Quality Determination for Gate Delay Fault Tests Considering Three-State Elements.

Frank Poehl, Walter Anheier

J. Electron. Test., 1999

Effiziente Methoden zum Zahlenvergleich und zur Vorzeichenerkennung in Restklassensystemen.

Heiko Henkelmann, C. Bruennlein, Walter Anheier

Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 1999

Efficient VLSI implementation of modern symmetric block ciphers.

A. Schubert, Walter Anheier

Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

Implementation of sign detection in RNS using mixed radix representation.

Heiko Henkelmann, Walter Anheier

Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

1998

A Residue Number Arithmetic based Circuit for Pipelined Computation of Autocorrelation Coefficients of Speech Signal.

Ansgar Drolshagen, Walter Anheier, C. Chandra Sekhar

Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

1997

Processor Elements for the Standard Cell Implementation of Residue Number Systems.

Ansgar Drolshagen, Heiko Henkelmann, Walter Anheier

Proceedings of the 1997 International Conference on Application-Specific Systems, 1997

1995

Distributed automatic test pattern generation with a parallel FAN algorithm.

Stefan Radtke, Jens Bargfrede, Walter Anheier

Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

1994

An image analysis system for automatic data acquisition from colored scanned maps.

Norbert Ebi, Bernd Lauterbach, Walter Anheier

Mach. Vis. Appl., 1994

Segmentation of Scanned Maps in Uniform Color Spaces.

Bernd Lauterbach, Walter Anheier

Proceedings of IAPR Workshop on Machine Vision Applications, 1994

A New Strategy for Test Pattern Generation in Sequential Circuits.

Beom-Ik Cheon, Walter Anheier, Rainer Laur

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

1993

Segmentierung farbiger kartographischer Vorlagen in empfindungsgemäßen Farbräumen.

B. Lauerbach, Walter Anheier

Proceedings of the Mustererkennung 1993, 1993