Walid A. Najjar

According to our database, Walid A. Najjar authored at least 139 papers between 1987 and 2021.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of two.

2021

Efficient local locking for massively multithreaded in-memory hash-based operators.

Bashar Romanous, Skyler Windh, Ildar Absalyamov, Prerna Budhkar, Robert J. Halstead, Walid A. Najjar, Vassilis J. Tsotras

VLDB J., 2021

Acceleration of Parallel-Blocked QR Decomposition of Tall-and-Skinny Matrices on FPGAs.

Jose M. Rodriguez Borbon, Junjie Huang, Bryan M. Wong, Walid A. Najjar

ACM Trans. Archit. Code Optim., 2021

2020

Heterogeneous Acceleration of HAR Applications.

Jose M. Rodriguez Borbon, Xiaoyin Ma, Amit K. Roy-Chowdhury, Walid A. Najjar

IEEE Trans. Circuits Syst. Video Technol., 2020

High-Performance Parallel Radix Sort on FPGA.

Bashar Romanous, Mohammadreza Rezvani, Junjie Huang, Daniel Wong, Evangelos E. Papalexakis, Vassilis J. Tsotras, Walid A. Najjar

Proceedings of the 28th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2020

2019

PDES-A: Accelerators for Parallel Discrete Event Simulation Implemented on FPGAs.

Shafiur Rahman, Nael B. Abu-Ghazaleh, Walid A. Najjar

ACM Trans. Model. Comput. Simul., 2019

Accelerating In-Memory Database Selections Using Latency Masking Hardware Threads.

Prerna Budhkar, Ildar Absalyamov, Vasileios Zois, Skyler Windh, Walid A. Najjar, Vassilis J. Tsotras

ACM Trans. Archit. Code Optim., 2019

Efficient Main-Memory Top-K Selection For Multicore Architectures.

Vasileios Zois, Vassilis J. Tsotras, Walid A. Najjar

Proc. VLDB Endow., 2019

GPU Accelerated Top-K Selection With Efficient Early Stopping.

Vasileios Zois, Vassilis J. Tsotras, Walid A. Najjar

Proceedings of the 10th International Workshop on Accelerating Analytics and Data Management Systems Using Modern Processor and Storage Architectures, 2019

2018

Massively parallel skyline computation for processing-in-memory architectures.

Vasileios Zois, Divya Gupta, Vassilis J. Tsotras, Walid A. Najjar, Jean-François Roy

Proceedings of the 27th International Conference on Parallel Architectures and Compilation Techniques, 2018

2017

PDES-A: a Parallel Discrete Event Simulation Accelerator for FPGAs.

Shafiur Rahman, Nael B. Abu-Ghazaleh, Walid A. Najjar

Proceedings of the 2017 ACM SIGSIM Conference on Principles of Advanced Discrete Simulation, 2017

2016

Optimizing hardware design for Human Action Recognition.

Xiaoyin Ma, Jose M. Rodriguez Borbon, Walid A. Najjar, Amit K. Roy-Chowdhury

Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

Preface.

Paolo Ienne, Walid A. Najjar, Jason Helge Anderson, Philip Brisk, Walter Stechele

Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

FPGA-accelerated group-by aggregation using synchronizing caches.

Ildar Absalyamov, Prerna Budhkar, Skyler Windh, Robert J. Halstead, Walid A. Najjar, Vassilis J. Tsotras

Proceedings of the 12th International Workshop on Data Management on New Hardware, 2016

ROCCC 2.0.

Walid A. Najjar, Jason R. Villarreal, Robert J. Halstead

Proceedings of the FPGAs for Software Programmers, 2016

2015

Evaluation and Acceleration of High-Throughput Fixed-Point Object Detection on FPGAs.

Xiaoyin Ma, Walid A. Najjar, Amit K. Roy-Chowdhury

IEEE Trans. Circuits Syst. Video Technol., 2015

FHAST: FPGA-Based Acceleration of Bowtie in Hardware.

Edward B. Fernandez, Jason R. Villarreal, Stefano Lonardi, Walid A. Najjar

IEEE ACM Trans. Comput. Biol. Bioinform., 2015

High-Level Language Tools for Reconfigurable Computing.

Skyler Windh, Xiaoyin Ma, Robert J. Halstead, Prerna Budhkar, Zabdiel Luna, Omar Hussaini, Walid A. Najjar

Proc. IEEE, 2015

High performance FPGA and GPU complex pattern matching over spatio-temporal streams.

Roger Moussalli, Ildar Absalyamov, Marcos R. Vieira, Walid A. Najjar, Vassilis J. Tsotras

GeoInformatica, 2015

CAMs as Synchronizing Caches for Multithreaded Irregular Applications on FPGAs.

Skyler Windh, Prerna Budhkar, Walid A. Najjar

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

FPGA-based Multithreading for In-Memory Hash Joins.

Robert J. Halstead, Ildar Absalyamov, Walid A. Najjar, Vassilis J. Tsotras

Proceedings of the Seventh Biennial Conference on Innovative Data Systems Research, 2015

2014

A study on parallelizing XML path filtering using accelerators.

Roger Moussalli, Mariam Salloum, Robert J. Halstead, Walid A. Najjar, Vassilis J. Tsotras

ACM Trans. Embed. Comput. Syst., 2014

Reconfigurable Computing.

Walid A. Najjar, Paolo Ienne

IEEE Micro, 2014

Compiling irregular applications for reconfigurable systems.

Robert J. Halstead, Jason R. Villarreal, Walid A. Najjar

Int. J. High Perform. Comput. Netw., 2014

High-Throughput Fixed-Point Object Detection on FPGAs.

Xiaoyin Ma, Walid A. Najjar, Amit K. Roy-Chowdhury

Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

2013

High-Performance XML Twig Filtering using GPUs.

Ildar Absalyamov, Roger Moussalli, Vassilis J. Tsotras, Walid A. Najjar

Proceedings of the International Workshop on Accelerating Data Management Systems Using Modern Processor and Storage Architectures, 2013

Stream-Mode FPGA Acceleration of Complex Pattern Trajectory Querying.

Roger Moussalli, Marcos R. Vieira, Walid A. Najjar, Vassilis J. Tsotras

Proceedings of the Advances in Spatial and Temporal Databases, 2013

A High Throughput No-Stall Golomb-Rice Hardware Decoder.

Roger Moussalli, Walid A. Najjar, Xi Luo, Amna Khan

Proceedings of the 21st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2013

FPGA code accelerators - the compiler perspective.

Walid A. Najjar, Jason R. Villarreal

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Compiled multithreaded data paths on FPGAs for dynamic workloads.

Robert J. Halstead, Walid A. Najjar

Proceedings of the International Conference on Compilers, 2013

Efficient near-duplicate document detection using FPGAs.

Xi Luo, Walid A. Najjar, Vagelis Hristidis

Proceedings of the 2013 IEEE International Conference on Big Data (IEEE BigData 2013), 2013

2012

Multithreaded FPGA acceleration of DNA sequence mapping.

Edward Fernandez, Walid A. Najjar, Stefano Lonardi, Jason R. Villarreal

Proceedings of the IEEE Conference on High Performance Extreme Computing, 2012

2011

Efficient XML Path Filtering Using GPUs.

Roger Moussalli, Robert J. Halstead, Mariam Salloum, Walid A. Najjar, Vassilis J. Tsotras

Proceedings of the International Workshop on Accelerating Data Management Systems Using Modern Processor and Storage Architectures, 2011

Exploring irregular memory accesses on FPGAs.

Robert J. Halstead, Jason R. Villarreal, Walid A. Najjar

Proceedings of the first workshop on Irregular applications: architectures and algorithm, 2011

Massively parallel XML twig filtering using dynamic programming on FPGAs.

Roger Moussalli, Mariam Salloum, Walid A. Najjar, Vassilis J. Tsotras

Proceedings of the 27th International Conference on Data Engineering, 2011

String Matching in Hardware Using the FM-Index.

Edward Fernandez, Walid A. Najjar, Stefano Lonardi

Proceedings of the IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines, 2011

2010

Impact of high-level transformations within the ROCCC framework.

Betul Buyukkurt, John Cortes, Jason R. Villarreal, Walid A. Najjar

ACM Trans. Archit. Code Optim., 2010

Accelerating Dynamic Time Warping Subsequence Search with GPUs and FPGAs.

Doruk Sart, Abdullah Mueen, Walid A. Najjar, Eamonn J. Keogh, Vit Niennattrakul

Proceedings of the ICDM 2010, 2010

Accelerating XML Query Matching through Custom Stack Generation on FPGAs.

Roger Moussalli, Mariam Salloum, Walid A. Najjar, Vassilis J. Tsotras

Proceedings of the High Performance Embedded Architectures and Compilers, 2010

Exploration of Short Reads Genome Mapping in Hardware.

Edward Fernandez, Walid A. Najjar, Elena Yavorska Harris, Stefano Lonardi

Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

Designing Modular Hardware Accelerators in C with ROCCC 2.0.

Jason R. Villarreal, Adrian Park, Walid A. Najjar, Robert J. Halstead

Proceedings of the 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2010

2009

Energy-efficient encoding techniques for off-chip data buses.

Dinesh C. Suresh, Banit Agrawal, Jun Yang, Walid A. Najjar

ACM Trans. Embed. Comput. Syst., 2009

Tunable and Energy Efficient Bus Encoding Techniques.

Dinesh C. Suresh, Banit Agrawal, Jun Yang, Walid A. Najjar

IEEE Trans. Computers, 2009

Boosting XML Filtering with a Scalable FPGA-based Architecture

Abhishek Mitra, Marcos R. Vieira, Petko Bakalov, Walid A. Najjar, Vassilis J. Tsotras

CoRR, 2009

Reconfigurable Computing in the New Age of Parallelism.

Walid A. Najjar, Jason R. Villarreal

Proceedings of the Embedded Computer Systems: Architectures, 2009

Boosting XML filtering through a scalable FPGA-based architecture.

Abhishek Mitra, Marcos R. Vieira, Petko Bakalov, Vassilis J. Tsotras, Walid A. Najjar

Proceedings of the Fourth Biennial Conference on Innovative Data Systems Research, 2009

2008

Efficient hardware code generation for FPGAs.

Zhi Guo, Walid A. Najjar, Betul Buyukkurt

ACM Trans. Archit. Code Optim., 2008

OpenFPGA CoreLib core library interoperability effort.

Michael J. Wirthlin, Daniel S. Poznanovic, P. Sundararajan, Alan J. Coppola, D. Pellerin, Walid A. Najjar, R. Bruce, M. Babst, O. Pritchard, Paolo Palazzari, Georgi Kuzmanov

Parallel Comput., 2008

A Compiler Intermediate Representation for Reconfigurable Fabrics.

Zhi Guo, Betul Buyukkurt, John Cortes, Abhishek Mitra, Walid A. Najjar

Int. J. Parallel Program., 2008

Compiled hardware acceleration of Molecular Dynamics code.

Jason R. Villarreal, Walid A. Najjar

Proceedings of the FPL 2008, 2008

Compiler generated systolic arrays for wavefront algorithm acceleration on FPGAs.

Betul Buyukkurt, Walid A. Najjar

Proceedings of the FPL 2008, 2008

2007

Dynamic Partial FPGA Reconfiguration in a Prototype Microprocessor System.

Kai Schleupen, Scott Lekuch, Ryan Mannion, Zhi Guo, Walid A. Najjar, Frank Vahid

Proceedings of the FPL 2007, 2007

A one-shot configurable-cache tuner for improved energy and performance.

Ann Gordon-Ross, Pablo Viana, Frank Vahid, Walid A. Najjar, Edna Barros

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Compiling code accelerators for FPGAs.

Walid A. Najjar

Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007

Compiling PCRE to FPGA for accelerating SNORT IDS.

Abhishek Mitra, Walid A. Najjar, Laxmi N. Bhuyan

Proceedings of the 2007 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, 2007

2006

Efficient indexing data structures for flash-based sensor devices.

Song Lin, Demetrios Zeinalipour-Yazti, Vana Kalogeraki, Dimitrios Gunopulos, Walid A. Najjar

ACM Trans. Storage, 2006

Compile-time area estimation for LUT-based FPGAs.

Dhananjay Kulkarni, Walid A. Najjar, Robert Rinker, Fadi J. Kurdahi

ACM Trans. Design Autom. Electr. Syst., 2006

Dynamic Co-Processor Architecture for Software Acceleration on CSoCs.

Abhishek Mitra, Zhi Guo, Anirban Banerjee, Walid A. Najjar

Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

A code refinement methodology for performance-improved synthesis from C.

Greg Stitt, Frank Vahid, Walid A. Najjar

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

A Compiler Intermediate Representation for Reconfigurable Fabrics.

Zhi Guo, Walid A. Najjar

Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Automation of IP Core Interface Generation for Reconfigurable Computing.

Zhi Guo, Abhishek Mitra, Walid A. Najjar

Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Automatic Compilation Framework for Bloom Filter Based Intrusion Detection.

Dinesh C. Suresh, Zhi Guo, Betul Buyukkurt, Walid A. Najjar

Proceedings of the Reconfigurable Computing: Architectures and Applications, 2006

Impact of Loop Unrolling on Area, Throughput and Clock Frequency in ROCCC: C to VHDL Compiler for FPGAs.

Betul Buyukkurt, Zhi Guo, Walid A. Najjar

Proceedings of the Reconfigurable Computing: Architectures and Applications, 2006

2005

A highly configurable cache for low energy embedded systems.

Chuanjun Zhang, Frank Vahid, Walid A. Najjar

ACM Trans. Embed. Comput. Syst., 2005

Splitting the sensor node.

Anirban Banerjee, Anirban Mitra, Walid A. Najjar

Proceedings of the 3rd International Conference on Embedded Networked Sensor Systems, 2005

RISE - Co-S : high performance sensor storage and Co-processing architecture.

Anirban Banerjee, Abhishek Mitra, Walid A. Najjar, Demetrios Zeinalipour-Yazti, Vana Kalogeraki, Dimitrios Gunopulos

Proceedings of the Second Annual IEEE Communications Society Conference on Sensor and Ad Hoc Communications and Networks, 2005

Power Efficient Instruction Caches for Embedded Systems.

Dinesh C. Suresh, Walid A. Najjar, Jun Yang

Proceedings of the Embedded Computer Systems: Architectures, 2005

Towards In-Situ Data Storage in Sensor Databases.

Demetrios Zeinalipour-Yazti, Vana Kalogeraki, Dimitrios Gunopulos, Anirban Mitra, Anirban Banerjee, Walid A. Najjar

Proceedings of the Advances in Informatics, 2005

A tunable bus encoder for off-chip data buses.

Dinesh C. Suresh, Banit Agrawal, Jun Yang, Walid A. Najjar

Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

Data Acquisition in Sensor Networks with Large Memories.

Demetrios Zeinalipour-Yazti, Vana Kalogeraki, Dimitrios Gunopulos, Walid A. Najjar

Proceedings of the 21st International Conference on Data Engineering Workshops, 2005

VALVE: Variable Length Value Encoder for Off-Chip Data Buses..

Dinesh C. Suresh, Banit Agrawal, Walid A. Najjar, Jun Yang

Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Techniques for synthesizing binaries to an advanced register/memory structure.

Greg Stitt, Zhi Guo, Walid A. Najjar, Frank Vahid

Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005

MicroHash: An Efficient Index Structure for Flash-Based Sensor Devices.

Demetrios Zeinalipour-Yazti, Song Lin, Vana Kalogeraki, Dimitrios Gunopulos, Walid A. Najjar

Proceedings of the FAST '05 Conference on File and Storage Technologies, 2005

Optimized Generation of Data-Path from C Codes for FPGAs.

Zhi Guo, Betul Buyukkurt, Walid A. Najjar, Kees A. Vissers

Proceedings of the 2005 Design, 2005

2004

Input data reuse in compiling window operations onto reconfigurable hardware.

Zhi Guo, Betul Buyukkurt, Walid A. Najjar

Proceedings of the 2004 ACM SIGPLAN/SIGBED Conference on Languages, 2004

"How Long is Your Belt?" Towards a Single Device for Multiple Functions.

Walid A. Najjar

Proceedings of the IEEE/ACS International Conference on Pervasive Services (ICPS'04), 2004

A quantitative analysis of the speedup factors of FPGAs over processors.

Zhi Guo, Walid A. Najjar, Frank Vahid, Kees A. Vissers

Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004

From Here to Main-stream: The Present and Future of Reconfigurable Computing.

Walid A. Najjar

Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, 2004

2003

Automatic compilation to a coarse-grained reconfigurable system-opn-chip.

Girish Venkataramani, Walid A. Najjar, Fadi J. Kurdahi, Nader Bagherzadeh, A. P. Wim Böhm, Jeffrey Hammes

ACM Trans. Embed. Comput. Syst., 2003

High-Level Language Abstraction for Reconfigurable Computing.

Walid A. Najjar, A. P. Wim Böhm, Bruce A. Draper, Jeffrey Hammes, Robert Rinker, J. Ross Beveridge, Monica Chawathe, Charles Ross

Computer, 2003

A Way-Halting Cache for Low-Energy High-Performance Systems.

Chuanjun Zhang, Frank Vahid, Jun Yang, Walid A. Najjar

IEEE Comput. Archit. Lett., 2003

Profiling tools for hardware/software partitioning of embedded applications.

Dinesh C. Suresh, Walid A. Najjar, Frank Vahid, Jason R. Villarreal, Greg Stitt

Proceedings of the 2003 Conference on Languages, 2003

Energy Benefits of a Configurable Line Size Cache for Embedded Systems.

Chuanjun Zhang, Frank Vahid, Walid A. Najjar

Proceedings of the 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), 2003

A Highly-Configurable Cache Architecture for Embedded Systems.

Chuanjun Zhang, Frank Vahid, Walid A. Najjar

Proceedings of the 30th International Symposium on Computer Architecture (ISCA 2003), 2003

FV-MSB: A Scheme for Reducing Transition Activity on Data Buses.

Dinesh C. Suresh, Jun Yang, Chuanjun Zhang, Banit Agrawal, Walid A. Najjar

Proceedings of the High Performance Computing - HiPC 2003, 10th International Conference, 2003

First results with eBlocks: embedded systems building blocks.

Susan Cotterell, Frank Vahid, Walid A. Najjar, Harry Hsieh

Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2003

Power efficient encoding techniques for off-chip data buses.

Dinesh C. Suresh, Banit Agrawal, Jun Yang, Walid A. Najjar, Laxmi N. Bhuyan

Proceedings of the International Conference on Compilers, 2003

2002

Mapping a Single Assignment Programming Language to Reconfigurable Systems.

A. P. Wim Böhm, Jeffrey Hammes, Bruce A. Draper, Monica Chawathe, Charlie Ross, Robert Rinker, Walid A. Najjar

J. Supercomput., 2002

Improving Software Performance with Configurable Logic.

Jason R. Villarreal, Dinesh C. Suresh, Greg Stitt, Frank Vahid, Walid A. Najjar

Des. Autom. Embed. Syst., 2002

Fast Area Estimation to Support Compiler Optimizations in FPGA-Based Reconfigurable Systems.

Dhananjay Kulkarni, Walid A. Najjar, Robert Rinker, Fadi J. Kurdahi

Proceedings of the 10th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2002), 2002

Compiling ATR Probing Codes for Execution on FPGA Hardware.

A. P. Wim Böhm, J. Ross Beveridge, Bruce A. Draper, Charlie Ross, Monica Chawathe, Walid A. Najjar

Proceedings of the 10th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2002), 2002

2001

An automated process for compiling dataflow graphs into reconfigurable hardware.

Robert Rinker, M. Carter, A. Patel, Monica Chawathe, Charlie Ross, Jeffrey Hammes, Walid A. Najjar, A. P. Wim Böhm

IEEE Trans. Very Large Scale Integr. Syst., 2001

A New Adaptive Hardware Tree-Based Multicast Routing in K-Ary N-Cubes.

Dianne R. Kumar, Walid A. Najjar, Pradip K. Srimani

IEEE Trans. Computers, 2001

Resource Management in Dataflow-Based Multithreaded Execution.

Lucas Roh, Bhanu Shankar, A. P. Wim Böhm, Walid A. Najjar

J. Parallel Distributed Comput., 2001

Performance Evaluation of a New Hardware Supported Multicast Scheme for K-ary N-cubes.

Dianne R. Kumar, Walid A. Najjar, Pradip K. Srimani

Proceedings of the 15th International Parallel & Distributed Processing Symposium (IPDPS-01), 2001

Loop fusion and temporal common subexpression elimination in window-based loops.

Jeffrey Hammes, A. P. Wim Böhm, Charlie Ross, Monica Chawathe, Bruce A. Draper, Robert Rinker, Walid A. Najjar

Proceedings of the 15th International Parallel & Distributed Processing Symposium (IPDPS-01), 2001

Compiling SA-C Programs to FPGAs: Performance Results.

Bruce A. Draper, A. P. Wim Böhm, Jeffrey Hammes, Walid A. Najjar, J. Ross Beveridge, Charlie Ross, Monica Chawathe, Mitesh Desai, José Bins

Proceedings of the Computer Vision Systems, Second International Workshop, 2001

One-Step Compilation of Image Processing Applications to FPGAs.

A. P. Wim Böhm, Bruce A. Draper, Walid A. Najjar, Jeffrey Hammes, Robert Rinker, Monica Chawathe, Charlie Ross

Proceedings of the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2001

The Sisal Project: Real World Functional Programming.

Jean-Luc Gaudiot, Thomas DeBoni, John Feo, A. P. Wim Böhm, Walid A. Najjar, Patrick Miller

Proceedings of the Compiler Optimizations for Scalable Parallel Systems Languages, 2001

A compiler framework for mapping applications to a coarse-grained reconfigurable computer architecture.

Girish Venkataramani, Walid A. Najjar, Fadi J. Kurdahi, Nader Bagherzadeh, A. P. Wim Böhm

Proceedings of the 2001 International Conference on Compilers, 2001

2000

A High Level, Algorithmic Programming Language and Compiler for Reconfigurable Systems.

Jeffrey Hammes, Robert Rinker, A. P. Wim Böhm, Walid A. Najjar, Bruce A. Draper

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2000

Compiling and Optimizing Image Processing Algorithms for FPGAs.

Bruce A. Draper, Walid A. Najjar, A. P. Wim Böhm, Jeffrey Hammes, Robert Rinker, Charlie Ross, Monica Chawathe, José Bins

Proceedings of the Fifth International Workshop on Computer Architectures for Machine Perception (CAMP 2000), 2000

Compiling Image Processing Applications to Reconfigurable Hardware.

Robert Rinker, Jeffrey Hammes, Walid A. Najjar, A. P. Wim Böhm, Bruce A. Draper

Proceedings of the 12th IEEE International Conference on Application-Specific Systems, 2000

1999

Advances in the dataflow computational model.

Walid A. Najjar, Edward A. Lee, Guang R. Gao

Parallel Comput., 1999

Combining Adaptive and Deterministic Routing: Evaluation of a Hybrid Router.

Dianne R. Kumar, Walid A. Najjar

Proceedings of the Network-Based Parallel Computing: Communication, 1999

Cameron: High level Language Compilation for Reconfigurable Systems.

Jeffrey Hammes, Robert Rinker, A. P. Wim Böhm, Walid A. Najjar, Bruce A. Draper, J. Ross Beveridge

Proceedings of the 1999 International Conference on Parallel Architectures and Compilation Techniques, 1999

1997

Foreword to the special issues.

Walid A. Najjar, Gabriel M. Silberman

Int. J. Parallel Program., 1997

Preliminary Evaluation of a Hybrid Deterministic/Adaptive Router.

Dianne Miller, Walid A. Najjar

Proceedings of the Parallel Computer Routing and Communication, 1997

Empirical Evaluation of Deterministic and Adaptive Routing with Constant-Area Routers.

Dianne Miller, Walid A. Najjar

Proceedings of the 1997 Conference on Parallel Architectures and Compilation Techniques (PACT '97), 1997

1996

Generation, Optimization, and Evaluation of Multithreaded Code.

Lucas Roh, Walid A. Najjar, Bhanu Shankar, A. P. Wim Böhm

J. Parallel Distributed Comput., 1996

Comparison of two storage models in data-driven multithreaded architectures.

Murali Annavaram, Walid A. Najjar

Proceedings of the Eighth IEEE Symposium on Parallel and Distributed Processing, 1996

Analysis of Buffer Design for Adaptive Routing in Direct Networks.

Annette Lagman, Walid A. Najjar

Proceedings of the MASCOTS '96, 1996

1995

Exploiting Data Structure Locality in the Dataflow Model.

William Marcus Miller, Walid A. Najjar, A. P. Wim Böhm

J. Parallel Distributed Comput., 1995

Design of storage hierarchy in multithreaded architectures.

Lucas Roh, Walid A. Najjar

Proceedings of the 28th Annual International Symposium on Microarchitecture, Ann Arbor, Michigan, USA, November 29, 1995

Control of loop parallelism in multithreaded code.

Bhanu Shankar, Lucas Roh, A. P. Wim Böhm, Walid A. Najjar

Proceedings of the IFIP WG10.3 working conference on Parallel architectures and compilation techniques, 1995

Analysis of communications and overhead reduction in multithreaded execution.

Lucas Roh, Walid A. Najjar

Proceedings of the IFIP WG10.3 working conference on Parallel architectures and compilation techniques, 1995

1994

Authors' Reply.

Walid A. Najjar, Jean-Luc Gaudiot

IEEE Trans. Computers, 1994

An Analysis of Edge Fault Tolerance in Recursively Decomposable Regular Networks.

Annette Lagman, Walid A. Najjar, Pradip K. Srimani

IEEE Trans. Computers, 1994

An evaluation of medium-grain dataflow code.

Walid A. Najjar, Lucas Roh, A. P. Wim Böhm

Int. J. Parallel Program., 1994

Modeling Adaptive Routing in <i>k</i>-ary <i>n</i>-cube Networks.

Walid A. Najjar, Annette Lagman, Sumit Sur, Pradip K. Srimani

Proceedings of the MASCOTS '94, Proceedings of the Second International Workshop on Modeling, Analysis, and Simulation On Computer and Telecommunication Systems, January 31, 1994

An Evaluation of Optimized Threaded Code Generation.

Lucas Roh, Walid A. Najjar, Bhanu Shankar, A. P. Wim Böhm

Proceedings of the Parallel Architectures and Compilation Techniques, 1994

A model for dataflow based vector execution.

William Marcus Miller, Walid A. Najjar, A. P. Wim Böhm

Proceedings of the 8th international conference on Supercomputing, 1994

Exploiting Locality in Hybrid Dataflow Programs.

Walid A. Najjar, A. P. Wim Böhm, William Marcus Miller

Proceedings of the Multithreaded Computer Architecture, 1994

1993

Conditional Disconnection Probability in Star Graphs.

Walid A. Najjar, Pradip K. Srimani

VLSI Design, 1993

A Quantitative Analysis of Dataflow Program Execution - Preliminaries to a Hybrid Design.

Walid A. Najjar, A. P. Wim Böhm, William Marcus Miller

J. Parallel Distributed Comput., 1993

Evaluation of Idealized Adaptive Routing on k-ary n-cubes.

Annette Lagman, Walid A. Najjar, Sumit Sur, Pradip K. Srimani

Proceedings of the Fifth IEEE Symposium on Parallel and Distributed Processing, 1993

An evaluation of bottom-up and top-down thread generation techniques.

A. P. Wim Böhm, Walid A. Najjar, Bhanu Shankar, Lucas Roh

Proceedings of the 26th Annual International Symposium on Microarchitecture, 1993

The Initial Performance of a Bottom-Up Clustering Algorithm for Dataflow Graphs.

Walid A. Najjar, Lucas Roh, A. P. Wim Böhm

Proceedings of the IFIP WG10.3. Working Conference on Architectures and Compilation Techniques for Fine and Medium Grain Parallelism, 1993

Generation and Quantitative Evaluation of Dataflow Clusters.

Lucas Roh, Walid A. Najjar, A. P. Wim Böhm

Proceedings of the conference on Functional programming languages and computer architecture, 1993

1992

An Analysis of Loop Latency in Dataflow Execution.

Walid A. Najjar, William Marcus Miller, A. P. Wim Böhm

Proceedings of the 19th Annual International Symposium on Computer Architecture. Gold Coast, 1992

1991

A Quantitative Analysis of Locality in Dataflow Programs.

William Marcus Miller, Walid A. Najjar, A. P. Wim Böhm

Proceedings of the 24th Annual IEEE/ACM International Symposium on Microarchitecture, 1991

Network resilience of star graphs: a comparative analysis.

Walid A. Najjar, Pradip K. Srimani

Proceedings of the 19th annual conference on Computer Science, 1991

1990

Network Resilience: A Measure of Network Fault Tolerance.

Walid A. Najjar, Jean-Luc Gaudiot

IEEE Trans. Computers, 1990

A data-driven execution paradigm for distributed fault-tolerance.

Walid A. Najjar, Jean-Luc Gaudiot

Proceedings of the 4th ACM SIGOPS European Workshop, Bologna, Italy, September 3-5, 1990, 1990

1989

Limits on Scalability in Gracefully Degradable Large-Scale Systems.

Walid A. Najjar, Jean-Luc Gaudiot

Proceedings of the Eigthth Symposium on Reliable Distributed Systems, 1989

A Single-Assignment Language in a Distributed Memory Multiprocessor.

Paraskevas Evripidou, Walid A. Najjar, Jean-Luc Gaudiot

Proceedings of the PARLE '89: Parallel Architectures and Languages Europe, 1989

1988

Network Disconnection in Distributed Systems.

Walid A. Najjar, Jean-Luc Gaudiot

Proceedings of the 8th International Conference on Distributed Computing Systems, 1988

1987

Parallel Discrete-Event Simulation.

Walid A. Najjar, Jean-Luc Jezouin, Jean-Luc Gaudiot

IEEE Des. Test, 1987

Reliability and Performance Modelling of Hypercube-Based Mutliprocessors.

Walid A. Najjar, Jean-Luc Gaudiot

Proceedings of the Computer Performance and Reliability, 1987

Multi-Level Execution In Data-Flow Architectures.

Walid A. Najjar, Jean-Luc Gaudiot

Proceedings of the International Conference on Parallel Processing, 1987