Waleed El-Halwagy

Orcid: 0000-0001-7666-4004

According to our database1, Waleed El-Halwagy authored at least 7 papers between 2013 and 2018.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2018
A 100-MS/s-5-GS/s, 13-5-bit Nyquist-Rate Reconfigurable Time-Domain ADC.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Investigation of Wideband Substrate-Integrated Vertically-Polarized Electric Dipole Antenna and Arrays for mm-Wave 5G Mobile Devices.
IEEE Access, 2018

2017
Fractional-N DPLL-Based Low-Power Clocking Architecture for 1-14 Gb/s Multi-Standard Transmitter.
IEEE J. Solid State Circuits, 2017

2016
Fractional-N DPLL based low power clocking architecture for 1-14 Gb/s multi-standard transmitter.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

A 79dB SNDR, 10MHz BW, 675MS/s open-loop time-based ADC employing a 1.15ps SAR-TDC.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2013
Analysis and design of analog-based voltage controlled oscillator linearization technique.
Proceedings of the 8th International Design and Test Symposium, 2013

A programmable 8-bit, 10MHz BW, 6.8mW, 200MSample/sec, 70dB SNDR VCO-based ADC using SC feedback for VCO linearization.
Proceedings of the 20th IEEE International Conference on Electronics, 2013


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