Wai Tung Ng

Orcid: 0000-0001-5952-2119

According to our database1, Wai Tung Ng authored at least 23 papers between 2000 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
A dual-mode digital controller with a high accuracy load current estimator and Gaussian adaptive duty cycle switching for fast transient recovery in DC-DC buck converters.
Comput. Electr. Eng., 2024

2021
A Self-Adaptive Measurement System for IGBT Collector Current Using Package Parasitics.
IEEE Trans. Ind. Electron., 2021

2020
Hybrid Buck Converter With Constant Mode Changing Point and Smooth Mode Transition for High-Frequency Applications.
IEEE Trans. Ind. Electron., 2020

2019
A Miniaturized Low-Intensity Ultrasound Device for Wearable Medical Therapeutic Applications.
IEEE Trans. Biomed. Circuits Syst., 2019

Smart Gate Driver ICs for GaN Power Transistors.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

An Inductive Power Transfer System With Adjustable Compensation Network For Implantable Medical Devices.
Proceedings of the 2019 IEEE Asia Pacific Conference on Circuits and Systems, 2019

2018
A high voltage multiplexer with rail to rail output swing for battery management system applications [IEICE Electronics Express Vol. 14(2017) No. 1 pp. 20161144].
IEICE Electron. Express, 2018

2017
A high voltage multiplexer with rail to rail output swing for battery management system applications.
IEICE Electron. Express, 2017

Design trends in smart gate driver ICs for power MOSFETs and IGBTs.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

2016
SPRUCE, an Embedded Compact Stack Machine for IGBT Power Modules.
Proceedings of the 46th IEEE International Symposium on Multiple-Valued Logic, 2016

2015
A Resistor-Based Sub-1-V CMOS Smart Temperature Sensor for VLSI Thermal Management.
IEEE Trans. Very Large Scale Integr. Syst., 2015

A Charge Recycling SAR ADC With a LSB-Down Switching Scheme.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

An all-digital self-calibrated delay-line based temperature sensor for VLSI thermal sensing and management.
Integr., 2015

2014
Delay-line temperature sensors and VLSI thermal management demonstrated on a 60nm FPGA.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013
A Power and Area Efficient 65 nm CMOS delay-Line ADC for on-Chip voltage Sensing.
J. Circuits Syst. Comput., 2013

A low power all-digital self-calibrated temperature sensor using 65nm FPGAs.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012
Study of the breakdown failure mechanisms for power AlGaN/GaN HEMTs implemented using a RF compatible process.
Microelectron. Reliab., 2012

A 0.02 nJ self-calibrated 65nm CMOS delay line temperature sensor.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011
Digitally Controlled Current-Mode DC-DC Converter IC.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

Versatile capabilities of digitally controlled integrated dc-dc converters.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2007
Design of a rugged 60 V VDMOS transistor.
IET Circuits Devices Syst., 2007

2005
Beamforming system for 3G and 4G wireless LAN applications.
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005

2000
A novel mixed-mode adaptive equalization system for high-speed 2-level PAM signals.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000


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