Wai Teng Tang

Orcid: 0000-0002-6553-1270

According to our database1, Wai Teng Tang authored at least 16 papers between 2004 and 2021.

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Bibliography

2021
DTNN: Energy-efficient Inference with Dendrite Tree Inspired Neural Networks for Edge Vision Applications.
CoRR, 2021

2020
An FPGA-Based Hardware Emulator for Neuromorphic Chip With RRAM.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Automatic detection of anatomical landmarks in brain MR scanning using multi-task deep neural networks.
Neurocomputing, 2020

2019
A System-Level Simulator for RRAM-Based Neuromorphic Computing Chips.
ACM Trans. Archit. Code Optim., 2019

2018
Exploiting Sparsity to Accelerate Fully Connected Layers of CNN-Based Applications on Mobile SoCs.
ACM Trans. Embed. Comput. Syst., 2018

2017
Scale-Free Sparse Matrix-Vector Multiplication on Many-Core Architectures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

2016
Automatic Segmentation of Left Ventricular Myocardium by Deep Convolutional and De-convolutional Neural Networks.
Proceedings of the Computing in Cardiology, CinC 2016, Vancouver, 2016

2015
A Family of Bit-Representation-Optimized Formats for Fast Sparse Matrix-Vector Multiplication on the GPU.
IEEE Trans. Parallel Distributed Syst., 2015

A Code Generation Framework for Targeting Optimized Library Calls for Multiple Platforms.
IEEE Trans. Parallel Distributed Syst., 2015

Optimizing and auto-tuning scale-free sparse matrix-vector multiplication on Intel Xeon Phi.
Proceedings of the 13th Annual IEEE/ACM International Symposium on Code Generation and Optimization, 2015

2013
Accelerating sparse matrix-vector multiplication on GPUs using bit-representation-optimized schemes.
Proceedings of the International Conference for High Performance Computing, 2013

Optimizing and Auto-Tuning Iterative Stencil Loops for GPUs with the In-Plane Method.
Proceedings of the 27th IEEE International Symposium on Parallel and Distributed Processing, 2013

2012
Automatic Refactoring of Legacy Fortran Code to the Array Slicing Notation.
Proceedings of the 18th IEEE International Conference on Parallel and Distributed Systems, 2012

Tulipse: A Visualization Framework for User-Guided Parallelization.
Proceedings of the Euro-Par 2012 Parallel Processing - 18th International Conference, 2012

2005
Ladder queue: An <i>O</i>(1) priority queue structure for large-scale discrete event simulation.
ACM Trans. Model. Comput. Simul., 2005

2004
The Demarcate Construction: A New Form of Tree-based Priority Queues.
Informatica (Slovenia), 2004


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