Wade L. Williams
According to our database1,
Wade L. Williams
authored at least 2 papers
between 2007 and 2009.
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Bibliography
2009
Loopback architecture for wafer-level at-speed testing of embedded HyperTransport<sup>TM</sup> processor links.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009
2007
Low Latency Clock Domain Transfer for Simultaneously Mesochronous, Plesiochronous and Heterochronous Interfaces.
Proceedings of the 13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2007), 2007