Vyacheslav Rovner

According to our database, Vyacheslav Rovner authored at least 6 papers between 2003 and 2010.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2010

Co-Optimization of Circuits, Layout and Lithography for Predictive Technology Scaling Beyond Gratings.

Tejas Jhaveri, Vyacheslav Rovner, Lars Liebmann, Larry T. Pileggi, Andrzej J. Strojwas, Jason Hibbeler

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

2009

Creating an affordable 22nm node using design-lithography co-optimization.

Andrzej J. Strojwas, Tejas Jhaveri, Vyacheslav Rovner, Lawrence T. Pileggi

Proceedings of the 46th Design Automation Conference, 2009

2005

Design methodology for IC manufacturability based on regular logic-bricks.

V. Kheterpal, Vyacheslav Rovner, T. G. Hersan, D. Motiani, Y. Takegawa, Andrzej J. Strojwas, Lawrence T. Pileggi

Proceedings of the 42nd Design Automation Conference, 2005

2004

Benchmarking Diagnosis Algorithms With a Diverse Set of IC Deformations.

Thomas J. Vogels, Thomas Zanon, Rao Desineni, R. D. (Shawn) Blanton, Wojciech Maly, Jason G. Brown, Jeffrey E. Nelson, Y. Fei, X. Huang, Padmini Gopalakrishnan, Mahim Mishra, Vyacheslav Rovner, S. Tiwary

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

2003

Exploring regular fabrics to optimize the performance-cost trade-off.

Lawrence T. Pileggi, Herman Schmit, Andrzej J. Strojwas, Padmini Gopalakrishnan, V. Kheterpal, Aneesh Koorapaty, Chetan Patel, Vyacheslav Rovner, Kim Yaw Tong

Proceedings of the 40th Design Automation Conference, 2003

Regular logic fabrics for a via patterned gate array (VPGA).

Kim Yaw Tong, V. Kheterpal, Vyacheslav Rovner, Lawrence T. Pileggi, Herman Schmit

Proceedings of the IEEE Custom Integrated Circuits Conference, 2003