Vyacheslav N. Yarmolik

According to our database, Vyacheslav N. Yarmolik authored at least 45 papers between 1983 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2022

Universal Address Sequence Generator for Memory Built-in Self-test.

Ireneusz Mrozek, Nikolai A. Shevchenko, Vyacheslav N. Yarmolik

Fundam. Informaticae, 2022

Synthesis of Test Sequences with a Given Switching Activity.

V. N. Yarmolik, Nikolai A. Shevchenko

Autom. Remote. Control., 2022

2021

Transparent Memory Tests Based on the Double Address Sequences.

Ireneusz Mrozek, Vyacheslav N. Yarmolik

Entropy, 2021

2018

Pseudo-Exhaustive Random Access Memory Testing Based on March Tests with Random Background Variation.

Ireneusz Mrozek, Vyacheslav N. Yarmolik

Proceedings of the 2018 IEEE East-West Design & Test Symposium, 2018

Multi-Run March Tests for Pattern Sensitive Faults in RAM.

Eugenia Buslowska, Vyacheslav N. Yarmolik

Proceedings of the 2018 IEEE East-West Design & Test Symposium, 2018

2017

Two-Run RAM March Testing with Address Decimation.

Ireneusz Mrozek, Vyacheslav N. Yarmolik

J. Circuits Syst. Comput., 2017

Optimal Controlled Random Tests.

Ireneusz Mrozek, Vyacheslav N. Yarmolik

Proceedings of the Computer Information Systems and Industrial Management, 2017

2016

Multiple Controlled Random Testing.

Ireneusz Mrozek, Vyacheslav N. Yarmolik

Fundam. Informaticae, 2016

Methods of Synthesis of Controlled Random Tests.

Ireneusz Mrozek, Vyacheslav N. Yarmolik

Proceedings of the Computer Information Systems and Industrial Management, 2016

2015

Controlled method of random test synthesis.

Vyacheslav N. Yarmolik, Ireneusz Mrozek, Svetlana V. Yarmolik

Autom. Control. Comput. Sci., 2015

2014

Address sequences.

Vyacheslav N. Yarmolik, Svetlana V. Yarmolik

Autom. Control. Comput. Sci., 2014

2013

Generating modified Sobol sequences for multiple run march memory tests.

V. N. Yarmolik, S. V. Yarmolik

Autom. Control. Comput. Sci., 2013

2012

Antirandom Test Vectors for BIST in Hardware/Software Systems.

Ireneusz Mrozek, Vyacheslav N. Yarmolik

Fundam. Informaticae, 2012

Iterative Antirandom Testing.

Ireneusz Mrozek, Vyacheslav N. Yarmolik

J. Electron. Test., 2012

2011

The synthesis of probability tests with a small number of kits.

S. V. Yarmolik, V. N. Yarmolik

Autom. Control. Comput. Sci., 2011

2010

Generalized adaptive signature analysis.

S. V. Yarmolik, Vyacheslav N. Yarmolik

Autom. Control. Comput. Sci., 2010

2009

Nondestructive RAM testing based on multiple signature comparison.

S. V. Yarmolik, V. N. Yarmolik

Autom. Control. Comput. Sci., 2009

2008

Determination of the optimal initial states for multiple-run RAM testing.

S. V. Yarmolik, Alexander N. Kurbatski, V. N. Yarmolik

Autom. Control. Comput. Sci., 2008

A new approach to the design of built-in internal memory self-testing devices.

A. A. Ivanyuk, V. N. Yarmolik

Autom. Control. Comput. Sci., 2008

Optimal Backgrounds Selection for Multi Run Memory Testing.

Ireneusz Mrozek, Vyacheslav N. Yarmolik

Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008

Multi Background Memory Testing.

Ireneusz Mrozek, Vyacheslav N. Yarmolik, Eugenia Buslowska

Proceedings of the 7th International Conference on Computer Information Systems and Industrial Management Applications, 2008

2007

Injection of functional faults in VHDL-description of digital devices.

A. A. Ivanyuk, V. N. Yarmolik

Autom. Control. Comput. Sci., 2007

Multiple Errors Detection Technique for RAM.

Sergei B. Musin, Alexander A. Ivaniuk, Vyacheslav N. Yarmolik

Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

Obfuscation as Intellectual Rights Protection in VHDL Language.

Maciej Brzozowski, Vyacheslav N. Yarmolik

Proceedings of the 6th International Conference on Computer Information Systems and Industrial Management Applications, 2007

2006

Designing cryptographic key generators with low power consumption.

Miroslaw Puczko, V. N. Yarmolik

Proceedings of the Third IEEE International Workshop on Electronic Design, 2006

2005

Cryptography and Steganography: teaching experience.

Bartosz Sokol, V. N. Yarmolik

Proceedings of the Enhanced Methods in Computer Security, 2005

Two-pattern test generation with low power consumption based on LFSR.

Miroslaw Puczko, V. N. Yarmolik

Proceedings of the Information Processing and Security Systems., 2005

2002

Efficient Online and Offline Testing of Embedded DRAMs.

Sybille Hellebrand, Hans-Joachim Wunderlich, Alexander A. Ivaniuk, Yuri V. Klimets, Vyacheslav N. Yarmolik

IEEE Trans. Computers, 2002

1999

Error Detecting Refreshment for Embedded DRAMs.

Sybille Hellebrand, Hans-Joachim Wunderlich, Alexander A. Ivaniuk, Yuri V. Klimets, Vyacheslav N. Yarmolik

Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

Transparent Word-Oriented Memory BIST Based on Symmetric March Algorithms.

Vyacheslav N. Yarmolik, I. V. Bykov, Sybille Hellebrand, Hans-Joachim Wunderlich

Proceedings of the Dependable Computing, 1999

Symmetric Transparent BIST for RAMs.

Sybille Hellebrand, Hans-Joachim Wunderlich, Vyacheslav N. Yarmolik

Proceedings of the 1999 Design, 1999

1998

BIST Module for Mixed-Signal Circuits.

Serge N. Demidenko, Vincenzo Piuri, Vyacheslav N. Yarmolik, A. Shmidman

Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 1998

Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs.

Vyacheslav N. Yarmolik, Sybille Hellebrand, Hans-Joachim Wunderlich

Proceedings of the 1998 Design, 1998

March PS(23N) Test for DRAM Pattern-Sensitive Faults.

Vyacheslav N. Yarmolik, Yuri V. Klimets, Serge N. Demidenko

Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

1997

March LA: a test for linked memory faults.

Ad J. van de Goor, Georgi Gaydadjiev, Vyacheslav N. Yarmolik, V. G. Mikitjuk

Proceedings of the European Design and Test Conference, 1997

1996

Transparent random access memory testing for pattern sensitive faults.

Mark G. Karpovsky, Vyacheslav N. Yarmolik

J. Electron. Test., 1996

March LR: a test for realistic linked faults.

Ad J. van de Goor, Georgi Gaydadjiev, V. G. Mikitjuk, Vyacheslav N. Yarmolik

Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

RAM Testing Algorithm for Detection Linked Coupling Faults.

V. G. Mikitjuk, V. N. Yarmolik, Ad J. van de Goor

Proceedings of the 1996 European Design and Test Conference, 1996

1995

Exact Aliasing Computation for RAM BIST.

O. Kebichi, Michael Nicolaidis, Vyacheslav N. Yarmolik

Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

Pseudo-exhaustive word-oriented DRAM testing.

Mark G. Karpovsky, Ad J. van de Goor, V. N. Yarmolik

Proceedings of the 1995 European Design and Test Conference, 1995

1994

Zero aliasing ROM BIST.

O. Kebichi, Vyacheslav N. Yarmolik, Michael Nicolaidis

J. Electron. Test., 1994

Aliasing-free Signature Analysis for RAM BIST.

Vyacheslav N. Yarmolik, Michael Nicolaidis, O. Kebichi

Proceedings of the Proceedings IEEE International Test Conference 1994, 1994

Transparent Memory Testing for Pattern-Sensitive Faults.

Mark G. Karpovsky, Vyacheslav N. Yarmolik

Proceedings of the Proceedings IEEE International Test Conference 1994, 1994

Signature Testability of PLA.

E. P. Kalosha, Vyacheslav N. Yarmolik, Mark G. Karpovsky

Proceedings of the Field-Programmable Logic, 1994

1983

Generator of randomized pseudorandom numbers.

Jan Havel, A. N. Morozevich, Vyacheslav N. Yarmolik

Kybernetika, 1983