Vladimir Rybalkin
Orcid: 0000-0002-0926-6062
According to our database1,
Vladimir Rybalkin
authored at least 17 papers
between 2015 and 2022.
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Bibliography
2022
Efficient hardware accleration of recurrent neural networks = Effiziente Hardwarebeschleunigung rekurrenter neuronaler Netze.
PhD thesis, 2022
When Massive GPU Parallelism Ain't Enough: A Novel Hardware Architecture of 2D-LSTM Neural Network.
ACM Trans. Reconfigurable Technol. Syst., 2022
2021
J. Signal Process. Syst., 2021
iDocChip: A Configurable Hardware Accelerator for an End-to-End Historical Document Image Processing.
J. Imaging, 2021
iDocChip: A Configurable Hardware Architecture for Historical Document Image Processing.
Int. J. Parallel Program., 2021
Proceedings of the Machine Learning and Principles and Practice of Knowledge Discovery in Databases, 2021
Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021
2020
J. Signal Process. Syst., 2020
When Massive GPU Parallelism Ain't Enough: A Novel Hardware Architecture of 2D-LSTM Neural Network.
Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020
2019
iDocChip - A Configurable Hardware Architecture for Historical Document Image Processing: Text Line Extraction.
Proceedings of the 2019 International Conference on ReConFigurable Computing and FPGAs, 2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
2018
FINN-L: Library Extensions and Design Trade-Off Analysis for Variable Precision LSTM Networks on FPGAs.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018
iDocChip: A Configurable Hardware Architecture for Historical Document Image Processing: Percentile Based Binarization.
Proceedings of the ACM Symposium on Document Engineering 2018, 2018
2017
Hardware architecture of Bidirectional Long Short-Term Memory Neural Network for Optical Character Recognition.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
2016
A New Architecture for High Speed, Low Latency NB-LDPC Check Node Processing for GF(256).
Proceedings of the IEEE 83rd Vehicular Technology Conference, 2016
2015
Proceedings of the 26th IEEE Annual International Symposium on Personal, 2015