Vladimir Herdt
Orcid: 0000-0002-4481-057X
According to our database1,
Vladimir Herdt
authored at least 69 papers
between 2013 and 2023.
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Bibliography
2023
Specification-Based Symbolic Execution for Stateful Network Protocol Implementations in IoT.
IEEE Internet Things J., June, 2023
Artifacts for the IEEE Internet of Things Journal Publication: Specification-based Symbolic Execution for Stateful Network Protocol Implementations in the IoT.
Dataset, January, 2023
Proceedings of the 15th International Conference on Agents and Artificial Intelligence, 2023
Identification of ISA-Level Mutation-Classes for Qualification of RISC-V Formal Verification.
Proceedings of the Forum on Specification & Design Languages, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
2022
Artifacts for the 2022 ATVA Paper: SISL: Concolic Testing of Structured Binary Input Formats via Partial Specification.
Dataset, July, 2022
SymEx-VP: An open source virtual prototype for OS-agnostic concolic testing of IoT firmware.
J. Syst. Archit., 2022
The MicroRV32 framework: An accessible and configurable open source RISC-V cross-level platform for education and research.
J. Syst. Archit., 2022
Towards Quantification and Visualization of the Effects of Concretization During Concolic Testing.
IEEE Embed. Syst. Lett., 2022
Advanced virtual prototyping for cyber-physical systems using RISC-V: implementation, verification and challenges.
Sci. China Inf. Sci., 2022
Proceedings of the 30th Mediterranean Conference on Control and Automation, 2022
Advanced Environment Modeling and Interaction in an Open Source RISC-V Virtual Prototype.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022
Proceedings of the Forum on Specification & Design Languages, 2022
Virtual Prototype based Analysis of Neural Network Cache Behavior for Tiny Edge Device.
Proceedings of the Forum on Specification & Design Languages, 2022
Unified HW/SW Coverage: A Novel Metric to Boost Coverage-guided Fuzzing for Virtual Prototype based HW/SW Co-Verification.
Proceedings of the Forum on Specification & Design Languages, 2022
Task Mapping and Scheduling in FPGA-based Heterogeneous Real-time Systems: A RISC-V Case-Study.
Proceedings of the 25th Euromicro Conference on Digital System Design, 2022
Virtual Prototype driven Design, Implementation and Evaluation of RISC-V Instruction Set Extensions.
Proceedings of the 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
Proceedings of the Automated Technology for Verification and Analysis, 2022
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022
2021
Artifacts for the FDL21 Paper: In-Vivo Stack Overflow Detection and Stack Size Estimation for Low-End Multithreaded Operating Systems using Virtual Prototypes.
Dataset, September, 2021
Adaptive simulation with Virtual Prototypes in an open-source RISC-V evaluation platform.
J. Syst. Archit., 2021
Metamorphic Testing for Processor Verification: A RISC-V Case Study at the Instruction Level.
Proceedings of the 29th IFIP/IEEE International Conference on Very Large Scale Integration, 2021
Proceedings of the Methods and Description Languages for Modelling and Verification of Circuits and Systems, 2021
In-Vivo Stack Overflow Detection and Stack Size Estimation for Low-End Multithreaded Operating Systems using Virtual Prototypes.
Proceedings of the 24th Forum on specification & Design Languages, 2021
Proceedings of the 24th Forum on specification & Design Languages, 2021
An Effective Methodology for Integrating Concolic Testing with SystemC-based Virtual Prototypes.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Towards Reliable Spatial Memory Safety for Embedded Software by Combining Checked C with Concolic Testing.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
2020
Proceedings of the Ausgezeichnete Informatikdissertationen 2020., 2020
RISC-V based virtual prototype: An extensible and configurable platform for the system-level.
J. Syst. Archit., 2020
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020
Verifying Safety Properties of Robotic Plans Operating in Real-World Environments via Logic-Based Environment Modeling.
Proceedings of the Leveraging Applications of Formal Methods, Verification and Validation: Applications, 2020
Adaptive Simulation with Virtual Prototypes for RISC-V: Switching Between Fast and Accurate at Runtime.
Proceedings of the 38th IEEE International Conference on Computer Design, 2020
Verification of Embedded Binaries using Coverage-guided Fuzzing with SystemC-based Virtual Prototypes.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020
Proceedings of the Forum for Specification and Design Languages, 2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Fast and Accurate Performance Evaluation for RISC-V using Virtual Prototypes<sup>*</sup>.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Dynamic Information Flow Tracking for Embedded Binaries using SystemC-based Virtual Prototypes.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
Closing the RISC-V Compliance Gap: Looking from the Negative Testing Side<sup>*</sup>.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
Proceedings of the Automated Technology for Verification and Analysis, 2020
2019
Efficient modeling, verification and analysis techniques to enhance the virtual prototype based design flow for embedded systems.
PhD thesis, 2019
Verifying SystemC Using Intermediate Verification Language and Stateful Symbolic Simulation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
Combining sequentialization-based verification of multi-threaded C programs with symbolic Partial Order Reduction.
Int. J. Softw. Tools Technol. Transf., 2019
Proceedings of the 2019 Forum for Specification and Design Languages, 2019
Towards Formal Verification of Plans for Cognition-Enabled Autonomous Robotic Agents.
Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Early Concolic Testing of Embedded Binaries with Virtual Prototypes: A RISC-V Case Study.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019
2018
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2018
Proceedings of the 2018 Forum on Specification & Design Languages, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
2017
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017
Towards Early Validation of Firmware-Based Power Management Using Virtual Prototypes: A Constrained Random Approach.
Proceedings of the Languages, Design Methods, and Tools for Electronic System Design, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
2016
Proceedings of the 35th International Conference on Computer-Aided Design, 2016
On the application of formal fault localization to automated RTL-to-TLM fault correspondence analysis for fast and accurate VP-based error effect simulation - a case study.
Proceedings of the 2016 Forum on Specification and Design Languages, 2016
Towards formal verification of real-world SystemC TLM peripheral models - a case study.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Proceedings of the Computer Aided Verification - 28th International Conference, 2016
Complete Symbolic Simulation of SystemC Models - Efficient Formal Verification of Finite Non-Terminating Programs
BestMasters, Springer, ISBN: 978-3-658-12680-3, 2016
2015
Proceedings of the 52nd Annual Design Automation Conference, 2015
Lazy-CSeq-SP: Boosting Sequentialization-Based Verification of Multi-threaded C Programs via Symbolic Pruning of Redundant Schedules.
Proceedings of the Automated Technology for Verification and Analysis, 2015
2013
Verifying SystemC using an intermediate verification language and symbolic simulation.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013