Vladimir Dimic

According to our database, Vladimir Dimic authored at least 4 papers between 2017 and 2021.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2021

PrioRAT: Criticality-Driven Prioritization Inside the On-Chip Memory Hierarchy.

Vladimir Dimic, Miquel Moretó, Marc Casas, Mateo Valero

Proceedings of the Euro-Par 2021: Parallel Processing, 2021

2020

Runtime-assisted optimizations in the on-chip memory hierarchy.

Vladimir Dimic

PhD thesis, 2020

RICH: implementing reductions in the cache hierarchy.

Vladimir Dimic, Miquel Moretó, Marc Casas, Jan Ciesko, Mateo Valero

Proceedings of the ICS '20: 2020 International Conference on Supercomputing, 2020

2017

Runtime-Assisted Shared Cache Insertion Policies Based on Re-reference Intervals.

Vladimir Dimic, Miquel Moretó, Marc Casas, Mateo Valero

Proceedings of the Euro-Par 2017: Parallel Processing - 23rd International Conference on Parallel and Distributed Computing, Santiago de Compostela, Spain, August 28, 2017