Viveka Konandur Rajanna

According to our database, Viveka Konandur Rajanna authored at least 14 papers between 2016 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

122.7 TOPS/W Stdcell-Based DNN Accelerator Based on Transition Density Data Representation, Clock-Less MAC Operation, Pseudo-Sparsity Exploitation in 40 nm.

Animesh Gupta, Japesh Vohra, Viveka Konandur Rajanna, Massimo Alioto

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

2023

Visual Content-Agnostic Novelty Detection Engine with 2.4 pJ/pixel Energy and Two-Order of Magnitude DNN Activity Reduction in 40 nm.

Animesh Gupta, Sayan Kumar, Viveka Konandur Rajanna, Sachin Taneja, Massimo Alioto

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

ECC-Less Multi-Level SRAM Physically Unclonable Function and 127% PUF-to-Memory Capacity Ratio with No Bitcell Modification in 28nm.

Joydeep Basu, Sachin Taneja, Viveka Konandur Rajanna, Tianqi Wang, Massimo Alioto

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

Energy-Efficient Computation in Constrained Systems with Machine Learning Workloads.

Viveka Konandur Rajanna

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2023

Single-Antenna Backscattered BLE5 Transmitter with up to 97m Range, 10.6 μW Peak Power for Purely-Harvested Green Systems.

Karim Ali Ahmed, Ruiyuan Yang, Praveenakumar Shivappa Salamani, Viveka Konandur Rajanna, Massimo Alioto

Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023

2022

In-Memory Unified TRNG and Multi-Bit PUF for Ubiquitous Hardware Security.

Sachin Taneja, Viveka Konandur Rajanna, Massimo Alioto

IEEE J. Solid State Circuits, 2022

Fully-Digital Broadband Calibration-Less Impedance Monitor for Probe Insertion Detection against Power Analysis Attacks.

Viveka Konandur Rajanna, Himadri Singh Raghav, Tianqi Wang, Massimo Alioto

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

DDPMnet: All-Digital Pulse Density-Based DNN Architecture with 228 Gate Equivalents/MAC Unit, 28-TOPS/W and 1.5-TOPS/mm2 in 40nm.

Animesh Gupta, Viveka Konandur Rajanna, Thoithoi Salam, Saurabh Jain, Orazio Aiello, Paolo Crovetti, Massimo Alioto

Proceedings of the IEEE Custom Integrated Circuits Conference, 2022

2021

On-Chip Links With Energy-Quality Tradeoff in Error-Resilient and Machine Learning Applications.

Viveka Konandur Rajanna, Massimo Alioto

IEEE J. Solid State Circuits, 2021

Fully-Digital Self-Calibrating Decoder with Sub-µW, 1.6fJ/convstep and 0.0075mm² per Receptor for Scaling to Human-Like Tactile Sensing Density.

Prachi Agarwal, Viveka Konandur Rajanna, Toh Wei Da, Benjamin C. K. Tee, Massimo Alioto

Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

36.1 Unified In-Memory Dynamic TRNG and Multi-Bit Static PUF Entropy Generation for Ubiquitous Hardware Security.

Sachin Taneja, Viveka Konandur Rajanna, Massimo Alioto

Proceedings of the IEEE International Solid-State Circuits Conference, 2021

SRAM with In-Memory Inference and 90% Bitline Activity Reduction for Always-On Sensing with 109 TOPS/mm² and 749-1, 459 TOPS/W in 28nm.

Viveka Konandur Rajanna, Sachin Taneja, Massimo Alioto

Proceedings of the 51st IEEE European Solid-State Device Research Conference, 2021

2019

Low-Swing Links with Dynamic Energy-Quality Trade-off for Error-Resilient Applications.

Viveka Konandur Rajanna, Massimo Alioto

Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

2016

A Variation-Tolerant Replica-Based Reference-Generation Technique for Single-Ended Sensing in Wide Voltage-Range SRAMs.

Viveka Konandur Rajanna, Bharadwaj Amrutur

IEEE Trans. Very Large Scale Integr. Syst., 2016