Vivek Joshi

Orcid: 0000-0001-7206-9988

According to our database1, Vivek Joshi authored at least 30 papers between 2006 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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On csauthors.net:

Bibliography

2022
Automated Labeling and Classification of Business Rules from Software Requirement Specifications.
Proceedings of the 44th IEEE/ACM International Conference on Software Engineering: Software Engineering in Practice, 2022

2021
Domain adaptation for an automated classification of deontic modalities in software engineering contracts.
Proceedings of the ESEC/FSE '21: 29th ACM Joint European Software Engineering Conference and Symposium on the Foundations of Software Engineering, 2021

Writaupair: Assistive Platform for Children with Writing Difficulties.
Proceedings of the 22nd IEEE International Conference on Information Reuse and Integration for Data Science, 2021

2020
Extracting and Classifying Requirements from Software Engineering Contracts.
Proceedings of the 28th IEEE International Requirements Engineering Conference, 2020

2019
Simulation Based Assessment of SRAM Data Retention Voltage.
Proceedings of the 20th International Symposium on Quality Electronic Design, 2019

Towards enhanced accountability in complying with healthcare regulations.
Proceedings of the 1st International Workshop on Software Engineering for Healthcare, 2019

2018
10T Differential-Signal SRAM Design in a L4-NM FinFET Technology for High-Speed Application.
Proceedings of the 31st IEEE International System-on-Chip Conference, 2018

MRI-based active shape model of the human proximal femur using fiducial and secondary landmarks and its validation.
Proceedings of the Medical Imaging 2018: Biomedical Applications in Molecular, 2018

Novel Back Gate Doping Ultra Low Retention Power 22nm FDSOl SRAM for IOT Application.
Proceedings of the 48th European Solid-State Device Research Conference, 2018

2016
Near-threshold circuit variability in 14nm FinFETs for ultra-low power applications.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

2015
Assessing intrinsic and extrinsic end-of-life risk using functional SRAM wafer level testing.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

SRAM Vmax stability considerations.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

2014
PACS Administrators' and Radiologists' Perspective on the Importance of Features for PACS Selection.
J. Digit. Imaging, 2014

HTOL SRAM Vmin shift considerations in scaled HKMG technologies.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013
SRAM read current variability and its dependence on transistor statistics.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012
Design-patterning co-optimization of SRAM robustness for double patterning lithography.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011
Empirical Investigation of Radiologists' Priorities for PACS Selection: An Analytical Hierarchy Process Approach.
J. Digit. Imaging, 2011

2010
Mechanical Stress Aware Optimization for Leakage Power Reduction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Simultaneous extraction of effective gate length and low-field mobility in non-uniform devices.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Analysis and optimization of SRAM robustness for double patterning lithography.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Closed-form modeling of layout-dependent mechanical stress.
Proceedings of the 47th Design Automation Conference, 2010

Analyzing the impact of Double Patterning Lithography on SRAM variability in 45nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

Analyzing electrical effects of RTA-driven local anneal temperature variation.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
Circuit optimization techniques to mitigate the effects of soft errors in combinational logic.
ACM Trans. Design Autom. Electr. Syst., 2009

IUF Scheduling Algorithm for Improving the Schedulability, Predictability and Sustainability of the Real Time System.
Proceedings of the Second International Conference on Emerging Trends in Engineering & Technology, 2009

2008
Stress aware layout optimization.
Proceedings of the 2008 International Symposium on Physical Design, 2008

STEEL: a technique for stress-enhanced standard cell library design.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Leakage power reduction using stress-enhanced layouts.
Proceedings of the 45th Design Automation Conference, 2008

2007
Soft-edge flip-flops for improved timing yield: design and optimization.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

2006
Logic SER Reduction through Flipflop Redesign.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006


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