Vivek Chickermane

According to our database, Vivek Chickermane authored at least 48 papers between 1990 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2024

The Future of Design for Test and Silicon Lifecycle Management.

Janusz Rajski, Vivek Chickermane, Jean-François Côté, Stephan Eggersglüß, Nilanjan Mukherjee, Jerzy Tyszer

IEEE Des. Test, August, 2024

2022

PPA Optimization of Test Points in Automotive Designs.

Brian Foutz, Sarthak Singhal, Prateek Kumar Rai, Krishna Chakravadhanula, Vivek Chickermane, Bharath Nandakumar, Sameer Chillarige, Christos Papameletis, Satish Ravichandran

Proceedings of the IEEE International Test Conference, 2022

2020

Guest Editors' Introduction: Selected Papers from IEEE VLSI Test Symposium.

Stefano Di Carlo, Peilin Song, Vivek Chickermane

IEEE Des. Test, 2020

2019

Observation Point Placement for Improved Logic Diagnosis based on Large Sets of Candidate Faults.

Irith Pomeranz, Vivek Chickermane, Srikanth Venkataraman

Proceedings of the 37th IEEE VLSI Test Symposium, 2019

Optimized Physical DFT Synthesis of Unified Compression and LBIST for Automotive Applications.

Christos Papameletis, Vivek Chickermane, Brian Foutz, Sarthak Singhal, Krishna Chakravadhanula

Proceedings of the IEEE International Test Conference, 2019

2017

Advancing test compression to the physical dimension.

Krishna Chakravadhanula, Vivek Chickermane, Paul Cunningham, Brian Foutz, Dale Meehl, Louis Milano, Christos Papameletis, David Scott, Steev Wilcox

Proceedings of the IEEE International Test Conference, 2017

2015

A DfT Architecture and Tool Flow for 3-D SICs With Test Data Compression, Embedded Cores, and Multiple Towers.

Christos Papameletis, Brion L. Keller, Vivek Chickermane, Said Hamdioui, Erik Jan Marinissen

IEEE Des. Test, 2015

A Novel Failure Diagnosis Approach for Low Pin Count and Low Power Compression Architectures.

Sameer Chillarige, S. Virdi, Anil Malik, Krishna Chakravadhanula, Vivek Chickermane, Joe Swenton, G. Vandling

Proceedings of the 24th IEEE North Atlantic Test Workshop, 2015

At-Speed Testing of Inter-Die Connections of 3D-SICs in the Presence of Shore Logic.

Konstantin Shibin, Vivek Chickermane, Brion L. Keller, Christos Papameletis, Erik Jan Marinissen

Proceedings of the 24th IEEE Asian Test Symposium, 2015

2014

Innovative practices session 1C: Existing/emerging low power techniques.

Charutosh Dixit, Ramesh C. Tekumalla, Wei Zhao, Nilanjan Mukherjee, Vivek Chickermane

Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

Tutorial T3A: Testing Low-Power Integrated Circuits: Challenges, Solutions, and Industry Practices.

Srivaths Ravi, Vivek Chickermane, Krishna Chakravadhanula

Proceedings of the 2014 27th International Conference on VLSI Design, 2014

Efficient testing of hierarchical core-based SOCs.

Brion L. Keller, Krishna Chakravadhanula, Brian Foutz, Vivek Chickermane, Akhil Garg, Richard Schoonover, James Sage, Don Pearl, Thomas J. Snethen

Proceedings of the 2014 International Test Conference, 2014

2013

Test and debug strategy for TSMC CoWoS™ stacking process based heterogeneous 3D IC: A silicon case study.

Sandeep Kumar Goel, Saman Adham, Min-Jer Wang, Ji-Jan Chen, Tze-Chiang Huang, Ashok Mehta, Frank Lee, Vivek Chickermane, Brion L. Keller, Thomas Valind, Subhasish Mukherjee, Navdeep Sood, Jeongho Cho, Hayden Hyungdong Lee, Jungi Choi, Sangdoo Kim

Proceedings of the 2013 IEEE International Test Conference, 2013

SmartScan - Hierarchical test compression for pin-limited low power designs.

Krishna Chakravadhanula, Vivek Chickermane, Don Pearl, Akhil Garg, R. Khurana, Subhasish Mukherjee, P. Nagaraj

Proceedings of the 2013 IEEE International Test Conference, 2013

Automated DfT insertion and test generation for 3D-SICs with embedded cores and multiple towers.

Christos Papameletis, Brion L. Keller, Vivek Chickermane, Erik Jan Marinissen, Said Hamdioui

Proceedings of the 18th IEEE European Test Symposium, 2013

2012

DfT architecture and ATPG for Interconnect tests of JEDEC Wide-I/O memory-on-logic die stacks.

Sergej Deutsch, Brion L. Keller, Vivek Chickermane, Subhasish Mukherjee, Navdeep Sood, Sandeep Kumar Goel, Ji-Jan Chen, Ashok Mehta, Frank Lee, Erik Jan Marinissen

Proceedings of the 2012 IEEE International Test Conference, 2012

2011

Automation of 3D-DfT Insertion.

Sergej Deutsch, Vivek Chickermane, Brion L. Keller, Subhasish Mukherjee, Mario Konijnenburg, Erik Jan Marinissen, Sandeep Kumar Goel

Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010

Low cost at-speed testing using On-Product Clock Generation compatible with test compression.

Brion L. Keller, Krishna Chakravadhanula, Brian Foutz, Vivek Chickermane, R. Malneedi, Thomas J. Snethen, Vikram Iyengar, David E. Lackey, Gary Grise

Proceedings of the 2011 IEEE International Test Conference, 2010

2009

Automating IEEE 1500 Core Test—An EDA Perspective.

Krishna Chakravadhanula, Vivek Chickermane

IEEE Des. Test Comput., 2009

Capture power reduction using clock gating aware test generation.

Krishna Chakravadhanula, Vivek Chickermane, Brion L. Keller, Patrick R. Gallagher Jr., Prashant Narang

Proceedings of the 2009 IEEE International Test Conference, 2009

Why is Conventional ATPG Not Sufficient for Advanced Low Power Designs?.

Krishna Chakravadhanula, Vivek Chickermane, Brion L. Keller, Patrick R. Gallagher Jr., Anis Uzzaman

Proceedings of the Eighteentgh Asian Test Symposium, 2009

2008

A Power-Aware Test Methodology for Multi-Supply Multi-Voltage Designs.

Vivek Chickermane, Patrick R. Gallagher Jr., James Sage, Paul Yuan, Krishna Chakravadhanula

Proceedings of the 2008 IEEE International Test Conference, 2008

Test Generation for State Retention Logic.

Krishna Chakravadhanula, Vivek Chickermane, Brion L. Keller, Patrick R. Gallagher Jr., Steven Gregor

Proceedings of the 17th IEEE Asian Test Symposium, 2008

2007

Low Power Reduced Pin Count Test Methodology.

Krishna Chakravadhanula, Nitin Parimi, Brian Foutz, Bing Li, Vivek Chickermane

Proceedings of the 16th Asian Test Symposium, 2007

2006

A Scalable Architecture for On-Chip Compression: Options and Trade-Offs.

Anis Uzzaman, Brion L. Keller, Vivek Chickermane

Proceedings of the 15th Asian Test Symposium, 2006

Early Life Cycle Yield Learning for Nanometer Devices Using Volume Yield Diagnostics Analysis.

Sanae Seike, Ken Namura, Yukio Ohya, Anis Uzzaman, Shinichi Arima, Dale Meehl, Vivek Chickermane, Azumi Kobayashi, Satoshi Tanaka, Hiroyuki Adachi

Proceedings of the 15th Asian Test Symposium, 2006

Automation of IEEE 1149.6 Boundary Scan Synthesis in an ASIC Methodology.

Brian Foutz, Vivek Chickermane, Bing Li, Harry Linzer, Gary Kunselman

Proceedings of the 15th Asian Test Symposium, 2006

2005

Low Cost Delay Testing of Nanometer SoCs Using On-Chip Clocking and Test Compression.

Hiroyuki Nakamura, Akio Shirokane, Yoshihito Nishizaki, Anis Uzzaman, Vivek Chickermane, Brion L. Keller, Tsutomu Ube, Yoshihiko Terauchi

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

Practical Aspects of Delay Testing for Nanometer Chips.

Vivek Chickermane, Brion L. Keller, Kevin McCauley, Anis Uzzaman

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2004

An Economic Analysis and ROI Model for Nanometer Test.

Brion L. Keller, Mick Tegethoff, Thomas Bartenstein, Vivek Chickermane

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Channel Masking Synthesis for Efficient On-Chip Test Compression.

Vivek Chickermane, Brian Foutz, Brion L. Keller

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

2001

System-on-Chip Testability Using LSSD Scan Structures.

Kamran Zarrineh, Shambhu J. Upadhyaya, Vivek Chickermane

IEEE Des. Test Comput., 2001

A building block BIST methodology for SOC designs: a case study.

Patrick R. Gallagher Jr., Vivek Chickermane, Steven Gregor, Thomas S. Pierre

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

2000

Integrating Logic BIST in VLSI Designs with Embedded Memories.

Vivek Chickermane, Scott Richter, Carl Barnhart

Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

1997

Addressing Early Design-For-Test Synthesis in a Production Environment.

Vivek Chickermane, Kamran Zarrineh

Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

1996

A Design For Test Perspective on I/O Management.

Kamran Zarrineh, Vivek Chickermane, Gareth Nicholls, Mike Palmer

Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996

1995

Sequential circuit testability enhancement using a nonscan approach.

Elizabeth M. Rudnick, Vivek Chickermane, Prithviraj Banerjee, Janak H. Patel

IEEE Trans. Very Large Scale Integr. Syst., 1995

1994

An observability enhancement approach for improved testability and at-speed test.

Elizabeth M. Rudnick, Vivek Chickermane, Janak H. Patel

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

Addressing design for testability at the architectural level.

Vivek Chickermane, Jaushin Lee, Janak H. Patel

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

1993

Impact of high level functional constraints on testability.

Jaushin Lee, Vivek Chickermane, Janak H. Patel

Proceedings of the 11th IEEE VLSI Test Symposium (VTS'93), 1993

Non-Scan Design-for-Testability Techniques for Sequential Circuits.

Vivek Chickermane, Elizabeth M. Rudnick, Prithviraj Banerjee, Janak H. Patel

Proceedings of the 30th Design Automation Conference. Dallas, 1993

1992

Probe point insertion for at-speed test.

Elizabeth M. Rudnick, Vivek Chickermane, Janak H. Patel

Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992

Design for Testability Using Architectural Descriptions.

Vivek Chickermane, Jaushin Lee, Janak H. Patel

Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

A comparative study of design for testability methods using high-level and gate-level descriptions.

Vivek Chickermane, Jaushin Lee, Janak H. Patel

Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

APT: An Area-Performance-Testability Driven Placement Algorithm.

Sungho Kim, Prithviraj Banerjee, Vivek Chickermane, Janak H. Patel

Proceedings of the 29th Design Automation Conference, 1992

1991

A Fault Oriented Partial Scan Design Approach.

Vivek Chickermane, Janak H. Patel

Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

Restructuring VLSI layout representations for efficiency.

Ravi Nair, Vivek Chickermane, Ray Chamberlain

Proceedings of the conference on European design automation, 1991

1990

An optimization based approach to the partial scan design problem.

Vivek Chickermane, Janak H. Patel

Proceedings of the Proceedings IEEE International Test Conference 1990, 1990