Viv A. Bartlett

According to our database, Viv A. Bartlett authored at least 15 papers between 1999 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2021

A VHDL-Based Modeling Approach for Rapid Functional Simulation and Verification of Adiabatic Circuits.

Sachin Maheshwari, Viv A. Bartlett, Izzet Kale

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

2020

Investigating the influence of adiabatic load on the 4-phase adiabatic system design.

Himadri Singh Raghav, V. A. Bartlett

Integr., 2020

2019

Modelling, simulation and verification of 4-phase adiabatic logic design: A VHDL-Based approach.

Sachin Maheshwari, Vivian A. Bartlett, Izzet Kale

Integr., 2019

2018

Investigating the effectiveness of Without Charge-Sharing Quasi-Adiabatic Logic for energy efficient and secure cryptographic implementations.

Himadri Singh Raghav, Vivian A. Bartlett, Izzet Kale

Microelectron. J., 2018

Energy efficient implementation of multi-phase quasi-adiabatic Cyclic Redundancy Check in near field communication.

Sachin Maheshwari, Vivian A. Bartlett, Izzet Kale

Integr., 2018

Symmetric Power Analysis Attack Resilient Adiabatic Logic for Smartcard Applications.

Himadri Singh Raghav, Vivian A. Bartlett, Izzet Kale

Proceedings of the 28th International Symposium on Power and Timing Modeling, 2018

VHDL-Based Modelling Approach for the Digital Simulation of 4-Phase Adiabatic Logic Design.

Sachin Maheshwari, Vivian A. Bartlett, Izzet Kale

Proceedings of the 28th International Symposium on Power and Timing Modeling, 2018

2017

Robustness of power analysis attack resilient adiabatic logic: WCS-QuAL under PVT variations.

Himadri Singh Raghav, Vivian A. Bartlett, Izzet Kale

Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017

A novel power analysis attack resilient adiabatic logic without charge sharing.

Himadri Singh Raghav, Vivian A. Bartlett, Izzet Kale

Proceedings of the 2017 European Conference on Circuit Theory and Design, 2017

Adiabatic flip-flops and sequential circuit design using novel resettable adiabatic buffers.

Sachin Maheshwari, Vivian A. Bartlett, Izzet Kale

Proceedings of the 2017 European Conference on Circuit Theory and Design, 2017

2016

Energy efficiency of 2-step charging power-clock for adiabatic logic.

Himadri Singh Raghav, Vivian A. Bartlett, Izzet Kale

Proceedings of the 26th International Workshop on Power and Timing Modeling, 2016

2001

Exploiting Data-dependencies in Ultra Low-power DSP Arithmetic.

V. A. Bartlett, Eckhard Grass

VLSI Design, 2001

Using carry-save adders in low-power multiplier blocks.

Viv A. Bartlett, Andrew G. Dempster

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

A Low-Power Asynchronous VLSI FIR Filter.

V. A. Bartlett, Eckhard Grass

Proceedings of the 19th Conference on Advanced Research in VLSI (ARVLSI 2001), 2001

1999

A low-power concurrent multiplier-accumulator using conditional evaluation.

V. A. Bartlett, Eckhard Grass

Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999