Vítor Grade Tavares

Orcid: 0000-0002-7567-0792

According to our database1, Vítor Grade Tavares authored at least 36 papers between 1998 and 2023.

Collaborative distances:

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2023
Depletion Based Digital and Analogue Circuits with n-Channel IGZO Thin Film Transistors.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

2021
A Switching-Mode Power Recycling System for a Radio-Frequency Outphasing Transmitter.
Proceedings of the XXXVI Conference on Design of Circuits and Integrated Systems, 2021

Trade-offs and Limitations in Energy-Efficient Inverter-based CMOS Amplifiers.
Proceedings of the XXXVI Conference on Design of Circuits and Integrated Systems, 2021

2020
A Multifunctional Integrated Circuit Router for Body Area Network Wearable Systems.
IEEE/ACM Trans. Netw., 2020

Recent activities by IEEE Education Society Portugal Chapter.
Proceedings of the 2020 IEEE Global Engineering Education Conference, 2020

Hardware architecture for integrate-and-fire signal reconstruction on FPGA.
Proceedings of the XXXV Conference on Design of Circuits and Integrated Systems, 2020

2019
IC Protection Against JTAG-Based Attacks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

2018
Analysis and Evaluation of anEnergy-Efficient Routing Protocol for WSNsCombining Source Routing and MinimumCost Forwarding.
J. Mobile Multimedia, 2018

Detection of IJTAG attacks using LDPC-based feature reduction and machine learning.
Proceedings of the 23rd IEEE European Test Symposium, 2018

2017
A Low-Power Analog Adder and Driver Using a-IGZO TFTs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

A complementary LC-tank based IR-UWB pulse generator for BPSK modulation.
Proceedings of the 2017 IEEE East-West Design & Test Symposium, 2017

2016
A small fully digital open-loop clock and data recovery circuit for wired BANs.
Int. J. Circuit Theory Appl., 2016

Basic analog and digital circuits with a-IGZO TFTs.
Proceedings of the 13th International Conference on Synthesis, 2016

A Learning-Based Approach to Secure JTAG Against Unseen Scan-Based Attacks.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Novel linear analog-adder using a-IGZO TFTs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015
A time synchronization circuit with sub-microsecond skew for multi-hop wired wearable networks.
Microprocess. Microsystems, 2015

Filter & hold: a mixed continuous-/discrete-time technique for time-constant scaling.
Int. J. Circuit Theory Appl., 2015

An Adaptive Signal Processing Framework for PV Power Maximization.
Circuits Syst. Signal Process., 2015

A low-power multi-tanh OTA with very low harmonic distortion.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Detection of illegitimate access to JTAG via statistical learning in chip.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

A fast spatial variation modeling algorithm for efficient test cost reduction of analog/RF circuits.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
Design considerations for LTCC based UWB antennas for space applications.
Proceedings of the 2014 IEEE International Conference on Wireless for Space and Extreme Environments, 2014

Transparent Current Mirrors Using a-GIZO TFTs: Simulation with RBF Models and Fabrication.
Proceedings of the UKSim-AMSS 16th International Conference on Computer Modelling and Simulation, 2014

Design and implementation of hybrid circuit/packet switching for wearable systems.
Proceedings of the 23rd IEEE International Symposium on Industrial Electronics, 2014

DALM-SVD: Accelerated sparse coding through singular value decomposition of the dictionary.
Proceedings of the 2014 IEEE International Conference on Image Processing, 2014

A Time Synchronization Circuit with an Average 4.6 ns One-Hop Skew for Wired Wearable Networks.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

2013
An adaptive duty-cycle methodology for PV power maximization using a single variable.
Proceedings of Eurocon 2013, 2013

High-gain topologies for transparent electronics.
Proceedings of Eurocon 2013, 2013

2012

BIST design for analog cell matching.
Proceedings of the 17th IEEE European Test Symposium, 2012

Proactive engineering.
Proceedings of the IEEE Global Engineering Education Conference, 2012

Design and Implementation of a Circuit for Mesh Networks with Application in Body Area Networks.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

2011
Network infrastructure for academic IC CAD environments.
Proceedings of EUROCON 2011, 2011

2001
Design and implementation of a biologically realistic olfactory cortex in analog VLSI.
Proc. IEEE, 2001

2000
A silicon olfactory bulb oscillator.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1998
Towards a silicon implementation of the olfactory system.
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998


  Loading...