Vishnuvardhan V. Iyer
Orcid: 0000-0002-9833-2710
According to our database1,
Vishnuvardhan V. Iyer
authored at least 7 papers
between 2019 and 2024.
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Bibliography
2024
A Hierarchical Classification Method for High-accuracy Instruction Disassembly with Near-field EM Measurements.
ACM Trans. Embed. Comput. Syst., January, 2024
Power and EM Side-Channel-Attack-Resilient AES-128 Core with Round-Aligned Globally-Synchronous-Locally-Asynchronous Operation Based on Tunable Replica Circuits.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2022
High-Level Simulation of Embedded Software Vulnerabilities to EM Side-Channel Attacks.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2022
2021
A Systematic Evaluation of EM and Power Side-Channel Analysis Attacks on AES Implementations.
Proceedings of the IEEE International Conference on Intelligence and Security Informatics, 2021
Galvanically Isolated, Power and Electromagnetic Side-Channel Attack Resilient Secure AES Core with Integrated Charge Pump based Power Management.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021
Physical Design Strategies for Mitigating Fine-Grained Electromagnetic Side-Channel Attacks.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021
2019
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2019