Vishnu P. Nambiar

According to our database, Vishnu P. Nambiar authored at least 30 papers between 2009 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

A 360 GOPS/W CGRA in a RISC-V SoC with Multi-Hop Routers and Idle-State Instructions for Edge Computing Applications.

Vishnu P. Nambiar, Y. S. Chong, Thilini Kaushalya Bandara, Dhananjaya Wijerathne, Z. Li, Rohan Juneja, Li-Shiuan Peh, Tulika Mitra, A. T. Do

Proceedings of the 21st International SoC Design Conference, 2024

3881 Gbps/W, 3005 µm AES Core with State Based Clock Gating for IoT applications.

Zhangyi Pei, Vishnu P. Nambiar, Yi Sheng Chong, Wang Ling Goh, Anh Tuan Do

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

Exploring Error Correction Circuits on RISC-V based Systems for Space Applications.

Nazim Altar Koca, Chip-Hong Chang, Anh Tuan Do, Vishnu P. Nambiar

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

A 420 GOPS/W CGRA with a Configurable MAC and Dynamic Truncation.

Yi Sheng Chong, Rakshith Harish, Rajesh Chandrasekhara Panicker, Vishnu P. Nambiar, Anh Tuan Do

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

Quantum Readout Processing Accelerator with a CORDIC Core at Cryogenic Temperature.

Yi Sheng Chong, Hongyu Cao, Wang Ling Goh, Patrick Bore, Yuanzheng Paul Tan, Yung Szen Yap, Rainer Dumke, Vishnu P. Nambiar, Anh Tuan Do

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

PACE: A Scalable and Energy Efficient CGRA in a RISC-V SoC for Edge Computing Applications.

Vishnu P. Nambiar, Yi Sheng Chong, Thilini Kaushalya Bandara, Dhananjaya Wijerathne, Zhaoying Li, Rohan Juneja, Li-Shiuan Peh, Tulika Mitra, Anh Tuan Do

Proceedings of the 36th IEEE Hot Chips Symposium, 2024

2022

A 2.5 μW KWS Engine With Pruned LSTM and Embedded MFCC for IoT Applications.

Yi Sheng Chong, Wang Ling Goh, Vishnu P. Nambiar, Anh-Tuan Do

IEEE Trans. Circuits Syst. II Express Briefs, 2022

A 1800μm², 953Gbps/W AES Accelerator for IoT Applications in 40nm CMOS.

Jingjing Lan, Vishnu P. Nambiar, Ming Ming Wong, Fei Li, Yuan Gao, Kevin Tshun Chuan Chai, Anh Tuan Do

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Recovering Accuracy of RRAM-based CIM for Binarized Neural Network via Chip-in-the-loop Training.

Yi Sheng Chong, Wang Ling Goh, Yew Soon Ong, Vishnu P. Nambiar, Anh Tuan Do

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

0.08mm² 128nW MFCC Engine for Ultra-low Power, Always-on Smart Sensing Applications.

Yi Sheng Chong, Wang Ling Goh, Yew Soon Ong, Vishnu P. Nambiar, Anh Tuan Do

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021

A Low Power and Low Area Router With Congestion-Aware Routing Algorithm for Spiking Neural Network Hardware Implementations.

Junran Pu, Wang Ling Goh, Vishnu P. Nambiar, Anh-Tuan Do

IEEE Trans. Circuits Syst. II Express Briefs, 2021

A Low-Cost High-Throughput Digital Design of Biorealistic Spiking Neuron.

Junran Pu, Wang Ling Goh, Vishnu P. Nambiar, Yi Sheng Chong, Anh Tuan Do

IEEE Trans. Circuits Syst. II Express Briefs, 2021

Energy Efficient 0.5V 4.8pJ/SOP 0.93μW Leakage/Core Neuromorphic Processor Design.

Vishnu P. Nambiar, Junran Pu, Yun Kwan Lee, Aarthy Mani, Eng-Kiat Koh, Ming Ming Wong, Fei Li, Wang Ling Goh, Anh Tuan Do

IEEE Trans. Circuits Syst. II Express Briefs, 2021

A 5.28-mm² 4.5-pJ/SOP Energy-Efficient Spiking Neural Network Hardware With Reconfigurable High Processing Speed Neuron Core and Congestion-Aware Router.

Junran Pu, Wang Ling Goh, Vishnu P. Nambiar, Ming Ming Wong, Anh Tuan Do

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Efficient Implementation of Activation Functions for LSTM accelerators.

Yi Sheng Chong, Wang Ling Goh, Yew Soon Ong, Vishnu P. Nambiar, Anh Tuan Do

Proceedings of the 29th IFIP/IEEE International Conference on Very Large Scale Integration, 2021

An Energy-Efficient Convolution Unit for Depthwise Separable Convolutional Neural Networks.

Yi Sheng Chong, Wang Ling Goh, Yew Soon Ong, Vishnu P. Nambiar, Anh Tuan Do

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

A 2.1 pJ/SOP 40nm SNN Accelerator Featuring On-chip Transfer Learning using Delta STDP.

Ming Ming Wong, S. B. Shrestha, Vishnu P. Nambiar, Aarthy Mani, Yun Kwan Lee, Eng-Kiat Koh, W. Jiang, Kevin Tshun Chuan Chai, Anh-Tuan Do

Proceedings of the 51st IEEE European Solid-State Device Research Conference, 2021

2020

Scalable Block-Based Spiking Neural Network Hardware with a Multiplierless Neuron Model.

Vishnu P. Nambiar, Eng-Kiat Koh, Junran Pu, Aarthy Mani, Ming Ming Wong, Li Fei, Wang Ling Goh, Anh Tuan Do

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Post-Silicon Validation Methodology for Resource-Constrained Neuromorphic Hardware.

Yun Kwan Lee, Vishnu P. Nambiar, Kim Seng Goh, Anh Tuan Do

Proceedings of the 46th Annual Conference of the IEEE Industrial Electronics Society, 2020

0.5V 4.8 pJ/SOP 0.93µW Leakage/core Neuromorphic Processor with Asynchronous NoC and Reconfigurable LIF Neuron.

Vishnu P. Nambiar, Junran Pu, Yun Kwan Lee, Aarthy Mani, Tao Luo, L. Yang, Eng-Kiat Koh, Ming Ming Wong, Fei Li, Wang Ling Goh, Anh Tuan Do

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2020

2019

Ower and Area Efficient Router with Automated Clock Gating for Neuromorphic Computing.

Junran Pu, Vishnu P. Nambiar, Aarthy Mani, Wang Ling Goh, Anh-Tuan Do

Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019

Coverage Driven Verification Methodology for Asynchronous Neuromorphic Routers.

Yun Kwan Lee, Vishnu P. Nambiar, Junran Pu, Wang Ling Goh, Anh-Tuan Do

Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019

Block-Based Spiking Neural Network Hardware with Deme Genetic Algorithm.

Junran Pu, Vishnu P. Nambiar, Anh-Tuan Do, Wang Ling Goh

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2017

A real-time near infrared image acquisition system based on image quality assessment.

Yee Hui Lee, Mohamed Khalil Hani, Rabia Bakhteri, Vishnu P. Nambiar

J. Real Time Image Process., 2017

2014

Hardware implementation of evolvable block-based neural networks utilizing a cost efficient sigmoid-like activation function.

Vishnu P. Nambiar, Mohamed Khalil Hani, Riadh Sahnoun, Muhammad N. Marsono

Neurocomputing, 2014

Optimization of structure and system latency in evolvable block-based neural networks using genetic algorithm.

Vishnu P. Nambiar, Mohamed Khalil Hani, Muhammad N. Marsono, Chen Wei Sia

Neurocomputing, 2014

2013

HW/SW co-design of reconfigurable hardware-based genetic algorithm in FPGAs applicable to a variety of problems.

Vishnu P. Nambiar, Sathivellu Balakrishnan, Mohamed Khalil Hani, Muhammad N. Marsono

Computing, 2013

Co-simulation methodology for improved design and verification of hardware neural networks.

Mohamed Khalil Hani, Vishnu P. Nambiar, Muhammad N. Marsono

Proceedings of the IECON 2013, 2013

2012

GA-based parameter tuning in finger-vein biometric embedded systems for information security.

Mohamed Khalil Hani, Vishnu P. Nambiar, Muhammad N. Marsono

Proceedings of the 2012 1st IEEE International Conference on Communications in China (ICCC), 2012

2009

Accelerating the AES encryption function in OpenSSL for embedded systems.

Vishnu P. Nambiar, Mohamed Khalil Hani, Muhammad Munim Ahmad Zabidi

Int. J. Inf. Commun. Technol., 2009