Vishal Suthar

Orcid: 0000-0002-9032-0715

According to our database1, Vishal Suthar authored at least 7 papers between 2004 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2022
Machine Learning Adoption in Blockchain-Based Smart Applications.
Proceedings of the 5th International Conference on Contemporary Computing and Informatics, 2022

2008
Built-in-Self-Test of FPGAs With Provable Diagnosabilities and High Diagnostic Coverage With Application to Online Testing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

2006
Mixed PLB and Interconnect BIST for FPGAs Without Fault-Free Assumptions.
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

A network-flow approach to timing-driven incremental placement for ASICs.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Efficient on-line interconnect testing in FPGAs with provable detectability for multiple faults.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005
High-diagnosability online built-in self-test of FPGAs via iterative bootstrapping.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

2004
Efficient on-line testing of FPGAs with provable diagnosabilities.
Proceedings of the 41th Design Automation Conference, 2004


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