Vishal Sharma

According to our database, Vishal Sharma authored at least 11 papers between 2018 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

A 1-Mb RRAM Macro With 9.8 ns Read Access Time Utilizing Dynamic Reference Voltage for Reliable Sensing Operation.

Junjie Mu, Lu Lu, Ju Eon Kim, Byung-Kwon An, Vishal Sharma, Arya Jagath Lekshmi, Putu Andhita Dananjaya, Weng Hong Lai, Wen Siang Lew, Tony Tae-Hyoung Kim

IEEE Trans. Circuits Syst. II Express Briefs, May, 2024

In-Memory Computing with 6T SRAM for Multi-operator Logic Design.

Narendra Singh Dhakad, Eshika Chittora, Gopal Raut, Vishal Sharma, Santosh Kumar Vishvakarma

Circuits Syst. Signal Process., January, 2024

2023

Designing a Performance-Centric MAC Unit with Pipelined Architecture for DNN Accelerators.

Gopal Raut, Jogesh Mukala, Vishal Sharma, Santosh Kumar Vishvakarma

Circuits Syst. Signal Process., October, 2023

A 400MHz 249.1TOPS/W 64Kb Fully-Reconfigurable SRAM-Based Digital Compute-in-Memory Macro for Accelerating CNNs.

Xin Zhang, Vishal Sharma, Yuncheng Lu, Yong-Jun Jo, Tony Tae-Hyoung Kim

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023

2022

A 64 Kb Reconfigurable Full-Precision Digital ReRAM-Based Compute-In-Memory for Artificial Intelligence Applications.

Vishal Sharma, Hyunjoon Kim, Tony Tae-Hyoung Kim

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

A Reconfigurable 16Kb AND8T SRAM Macro With Improved Linearity for Multibit Compute-In Memory of Artificial Intelligence Edge Devices.

Vishal Sharma, Ju Eon Kim, Hyunjoon Kim, Lu Lu, Tony Tae-Hyoung Kim

IEEE J. Emerg. Sel. Topics Circuits Syst., 2022

2021

AND8T SRAM Macro with Improved Linearity for Multi-Bit In-Memory Computing.

Vishal Sharma, Ju Eon Kim, Yong-Jun Jo, Yuzong Chen, Tony Tae-Hyoung Kim

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020

A 2.4-GS/s Power-Efficient, High-Resolution Reconfigurable Dynamic Comparator for ADC Architecture.

Gopal Raut, Ambika Prasad Shah, Vishal Sharma, Gunjan Rajput, Santosh Kumar Vishvakarma

Circuits Syst. Signal Process., 2020

ReRAM Device and Circuit Co-Design Challenges in Nano-scale CMOS Technology.

Lu Lu, Ju Eon Kim, Vishal Sharma, Tony Tae-Hyoung Kim

Proceedings of the 2020 IEEE Asia Pacific Conference on Circuits and Systems, 2020

2018

A write-improved low-power 12T SRAM cell for wearable wireless sensor nodes.

Vishal Sharma, Santosh Kumar Vishvakarma, Shailesh Singh Chouhan, Kari Halonen

Int. J. Circuit Theory Appl., 2018

A Write-Improved Half-Select-Free Low-Power 11T Subthreshold SRAM with Double Adjacent Error Correction for FPGA-LUT Design.

Vishal Sharma, Pranshu Bisht, Abhishek Dalal, Shailesh Singh Chouhan, H. S. Jattana, Santosh Kumar Vishvakarma

Proceedings of the VLSI Design and Test - 22nd International Symposium, 2018