Virinchi Roy Surabhi

Orcid: 0000-0002-8320-0045

According to our database1, Virinchi Roy Surabhi authored at least 11 papers between 2020 and 2024.

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Bibliography

2024
FEINT: Automated Framework for Efficient INsertion of Templates/Trojans into FPGAs.
Inf., July, 2024

2023
Golden-Free Robust Age Estimation to Triage Recycled ICs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., September, 2023

Multi-Modal Side Channel Data Driven Golden-Free Detection of Software and Firmware Trojans.
IEEE Trans. Dependable Secur. Comput., 2023

Comprehensive Reliability Analysis of 22nm FDSOI SRAM from Device Physics to Deep Learning.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

An Integrated Testbed for Trojans in Printed Circuit Boards with Fuzzing Capabilities.
Proceedings of the 29th International Symposium on On-Line Testing and Robust System Design, 2023

2022
Detecting Hardware Trojans in PCBs Using Side Channel Loopbacks.
IEEE Trans. Very Large Scale Integr. Syst., 2022

Trojan Detection in Embedded Systems With FinFET Technology.
IEEE Trans. Computers, 2022

2021
Learning Locomotion Controllers for Walking Using Deep FBSDE.
CoRR, 2021

2020
Exposing Hardware Trojans in Embedded Platforms via Short-Term Aging.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Hardware Trojan Detection Using Controlled Circuit Aging.
IEEE Access, 2020

Anomaly Detection in Embedded Systems Using Power and Memory Side Channels.
Proceedings of the IEEE European Test Symposium, 2020


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