Virendra Singh
Orcid: 0000-0002-7035-7844
According to our database1,
Virendra Singh
authored at least 165 papers
between 2003 and 2025.
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On csauthors.net:
Bibliography
2025
B-CAVE: A Robust Online Time Series Change Point Detection Algorithm Based on the Between-Class Average and Variance Evaluation Approach.
IEEE Trans. Knowl. Data Eng., January, 2025
2024
A-TSPD: autonomous-two stage algorithm for robust peak detection in online time series.
Clust. Comput., July, 2024
DAT: A robust Discriminant Analysis-based Test of unimodality for unknown input distributions.
Pattern Recognit. Lett., 2024
BD-MDLC: Behavior description-based enhanced malware detection for windows environment using longformer classifier.
Comput. Secur., 2024
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024
Proceedings of the 36th IEEE International Symposium on Computer Architecture and High Performance Computing, 2024
Proceedings of the International Symposium on Memory Systems, 2024
Proceedings of the Information Systems Security - 20th International Conference, 2024
Proceedings of the 16th International Conference on Agents and Artificial Intelligence, 2024
Proceedings of the 27th International Symposium on Design & Diagnostics of Electronic Circuits & Systems, 2024
2023
Proceedings of the IEEE International Conference on Service-Oriented System Engineering, 2023
Proceedings of the 24th IEEE Latin American Test Symposium, 2023
LUT-based Arithmetic Circuit Approximation with Formal Guarantee on Worst Case Relative Error.
Proceedings of the 24th IEEE Latin American Test Symposium, 2023
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2023
Proceedings of the 29th International Symposium on On-Line Testing and Robust System Design, 2023
Proceedings of the 29th International Symposium on On-Line Testing and Robust System Design, 2023
Proceedings of the 29th International Symposium on On-Line Testing and Robust System Design, 2023
Proceedings of the Information Systems Security - 19th International Conference, 2023
DDSR: An Online GPGPU Instruction Decoder Error Detecting and Correcting Architecture.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023
Proceedings of the 32nd IEEE Asian Test Symposium, 2023
2022
Comput. Ind. Eng., 2022
Exploiting post-silicon debug hardware to improve the fault coverage of Software Test Libraries.
Proceedings of the 40th IEEE VLSI Test Symposium, 2022
Scalable Construction of Formal Error Guaranteed LUT-Based Approximate Multipliers with Analytical Worst-Case Error Bound.
Proceedings of the VLSI Design and Test - 26th International Symposium, 2022
Disrupting Low-Write-Energy vs. Fast-Read Dilemma in RRAM to Enable L1 Instruction Cache.
Proceedings of the VLSI Design and Test - 26th International Symposium, 2022
Proceedings of the VLSI Design and Test - 26th International Symposium, 2022
Proceedings of the 19th International Conference on Security and Cryptography, 2022
REFU: Redundant Execution with Idle Functional Units, Fault Tolerant GPGPU architecture.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022
2021
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
J. Electron. Test., 2021
CoRR, 2021
IEEE Comput. Archit. Lett., 2021
IEEE Comput. Archit. Lett., 2021
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021
Proceedings of the IEEE International Conference on Advanced Networks and Telecommunications Systems, 2021
2020
A Methodology to Capture Fine-Grained Internal Visibility During Multisession Silicon Debug.
IEEE Trans. Very Large Scale Integr. Syst., 2020
Post-Silicon Gate-Level Error Localization With Effective and Combined Trace Signal Selection.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
IEEE Comput. Archit. Lett., 2020
A Low Overhead Methodology for Validating Memory Consistency Models in Chip Multiprocessors.
Proceedings of the 33rd International Conference on VLSI Design and 19th International Conference on Embedded Systems, 2020
Characterization of Data Generating Neural Network Applications on x86 CPU Architecture.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2020
Proceedings of the 29th IEEE Asian Test Symposium, 2020
2019
IET Comput. Digit. Tech., 2019
SAT-based Silicon Debug of Electrical Errors under Restricted Observability Enhancement.
J. Electron. Test., 2019
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019
A Methodology for SAT-Based Electrical Error Debugging During Post-Silicon Validation.
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019
Proceedings of the 20th International Symposium on Quality Electronic Design, 2019
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019
Proceedings of the 37th IEEE International Conference on Computer Design, 2019
Proceedings of the 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019
Orion: A Technique to Prune State Space Search Directions for Guidance-Based Formal Verification.
Proceedings of the 28th IEEE Asian Test Symposium, 2019
Validating Multi-Processor Cache Coherence Mechanisms under Diminished Observability.
Proceedings of the 28th IEEE Asian Test Symposium, 2019
2018
Multiple Stuck-at Fault Testability Analysis of ROBDD Based Combinational Circuit Design.
J. Electron. Test., 2018
Proceedings of the International Symposium on Memory Systems, 2018
Silicon Debug with Maximally Expanded Internal Observability Using Nearest Neighbor Algorithm.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
A Technique for Electrical Error Localization with Learning Methods During Post-silicon Debugging.
Proceedings of the Ninth International Green and Sustainable Computing Conference, 2018
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018
Proceedings of the 2018 IEEE East-West Design & Test Symposium, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
2017
J. Electron. Test., 2017
A Methodology for Trace Signal Selection to Improve Error Detection in Post-Silicon Validation.
Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017
Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017
Proceedings of the 2017 IFIP/IEEE International Conference on Very Large Scale Integration, 2017
Proceedings of the 18th IEEE Latin American Test Symposium, 2017
Proceedings of the 18th IEEE Latin American Test Symposium, 2017
Proceedings of the 18th IEEE Latin American Test Symposium, 2017
Exploiting path delay test generation to develop better TDF tests for small delay defects.
Proceedings of the IEEE International Test Conference, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Test pattern generation to detect multiple faults in ROBDD based combinational circuits.
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017
Revisiting random access scan for effective enhancement of post-silicon observability.
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017
RTL level trace signal selection and coverage estimation during post-silicon validation.
Proceedings of the 2017 IEEE International High Level Design Validation and Test Workshop, 2017
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017
Combining Restorability and Error Detection Ability for Effective Trace Signal Selection.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017
Proceedings of the 2017 IEEE East-West Design & Test Symposium, 2017
Proceedings of the 2017 IEEE East-West Design & Test Symposium, 2017
Proceedings of the 22nd IEEE European Test Symposium, 2017
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017
Proceedings of the 26th IEEE Asian Test Symposium, 2017
2016
REMO: Redundant execution with minimum area, power, performance overhead fault tolerant architecture.
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016
Proceedings of the 2016 IEEE East-West Design & Test Symposium, 2016
A technique for low power, stuck-at fault diagnosable and reconfigurable scan architecture.
Proceedings of the 2016 IEEE East-West Design & Test Symposium, 2016
Proceedings of the 2016 IEEE East-West Design & Test Symposium, 2016
Proceedings of the 2016 IEEE East-West Design & Test Symposium, 2016
Proceedings of the 2016 IEEE East-West Design & Test Symposium, 2016
Proceedings of the 2016 IEEE East-West Design & Test Symposium, 2016
2015
PDF testability of a combinational circuit derived by covering ROBDD nodes using Invert-And-Or circuits.
Proceedings of the 19th International Symposium on VLSI Design and Test, 2015
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015
Proceedings of the 24th IEEE Asian Test Symposium, 2015
Proceedings of the 24th IEEE Asian Test Symposium, 2015
Proceedings of the 24th IEEE Asian Test Symposium, 2015
2014
Evaluation of Level of Confidence and Optimization of Roll-back Recovery with Checkpointing for Real-Time Systems.
Microelectron. Reliab., 2014
Proceedings of the 2014 27th International Conference on VLSI Design, 2014
Proceedings of the 2014 East-West Design & Test Symposium, 2014
Proceedings of the 2014 East-West Design & Test Symposium, 2014
A data-driven adaptive model-identification based large-scale sensor management system: Application to self powered neutron detectors.
Proceedings of the 2014 IEEE Conference on Evolving and Adaptive Intelligent Systems, 2014
2013
Detection of false paths in logical circuits by joint analysis of the AND/OR trees and SSBDD-graphs.
Autom. Remote. Control., 2013
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013
Proceedings of the VLSI Design and Test, 17th International Symposium, 2013
Proceedings of the East-West Design & Test Symposium, 2013
Observability calculation of state variable oriented to robust PDFs and LOC or LOS techniques.
Proceedings of the East-West Design & Test Symposium, 2013
Proceedings of the East-West Design & Test Symposium, 2013
Proceedings of the East-West Design & Test Symposium, 2013
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013
2012
Parametric Fault Testing of Non-Linear Analog Circuits Based on Polynomial and V-Transform Coefficients.
J. Electron. Test., 2012
J. Electron. Test., 2012
Proceedings of the 30th IEEE VLSI Test Symposium, 2012
ILP Based Approach for Input Vector Controlled (IVC) Toggle Maximization in Combinational Circuits.
Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012
Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012
Efficient regular expression pattern matching for network intrusion detection systems using modified word-based automata.
Proceedings of the 5th International Conference of Security of Information and Networks, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Proceedings of the 18th IEEE International On-Line Testing Symposium, 2012
2011
Non-linear analog circuit test and diagnosis under process variation using V-Transform coefficients.
Proceedings of the 29th IEEE VLSI Test Symposium, 2011
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011
Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011
Proceedings of the 12th Latin American Test Workshop, 2011
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011
Proceedings of the IEEE 29th International Conference on Computer Design, 2011
Proceedings of the 13th IEEE International Conference on High Performance Computing & Communication, 2011
Proceedings of the 9th East-West Design & Test Symposium, 2011
Level of confidence evaluation and its usage for Roll-back Recovery with Checkpointing optimization.
Proceedings of the IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W 2011), 2011
Proceedings of the Sixth IEEE International Symposium on Electronic Design, 2011
Proceedings of the 20th IEEE Asian Test Symposium, 2011
Proceedings of the 20th IEEE Asian Test Symposium, 2011
2010
Parametric Fault Diagnosis of Nonlinear Analog Circuits Using Polynomial Coefficients.
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010
Genetic algorithm based topology generation for application specific Network-on-Chip.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Test application time minimization for RAS using basis optimization of column decoder.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010
Proceedings of the International Conference on Field-Programmable Technology, 2010
Proceedings of the 2010 East-West Design & Test Symposium, 2010
Proceedings of the 2010 East-West Design & Test Symposium, 2010
Proceedings of the 2010 East-West Design & Test Symposium, 2010
Proceedings of the 2010 East-West Design & Test Symposium, 2010
Proceedings of the 2010 East-West Design & Test Symposium, 2010
Scan cell reordering to minimize peak power during test cycle: A graph theoretic approach.
Proceedings of the 15th European Test Symposium, 2010
Proceedings of the 15th European Test Symposium, 2010
Energy-efficient fault tolerance in chip multiprocessors using Critical Value Forwarding.
Proceedings of the 2010 IEEE/IFIP International Conference on Dependable Systems and Networks, 2010
Estimating Error-probability and its Application for Optimizing Roll-back Recovery with Checkpointing.
Proceedings of the Fifth IEEE International Symposium on Electronic Design, 2010
Multiplexed redundant execution: A technique for efficient fault tolerance in chip multiprocessors.
Proceedings of the Design, Automation and Test in Europe, 2010
Proceedings of the 19th IEEE Asian Test Symposium, 2010
2009
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009
Proceedings of the 14th IEEE European Test Symposium, 2009
Fault-tolerant average execution time optimization for general-purpose multi-processor system-on-chips.
Proceedings of the Design, Automation and Test in Europe, 2009
Multi-tone Testing of Linear and Nonlinear Analog Circuits Using Polynomial Coefficients.
Proceedings of the Eighteentgh Asian Test Symposium, 2009
Leveraging Partially Enhanced Scan for Improved Observability in Delay Fault Testing.
Proceedings of the Eighteentgh Asian Test Symposium, 2009
2006
IEEE Trans. Very Large Scale Integr. Syst., 2006
2005
IEICE Trans. Inf. Syst., 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005
2004
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004
2003
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003