Vinod Menezes

Orcid: 0000-0001-5399-0851

According to our database1, Vinod Menezes authored at least 16 papers between 1996 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2022
A Multibit MAC Scheme using Switched Capacitor based 3C Multiplier for Analog Compute In-Memory Architecture.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022

2021
150nA IQ, Quad Input - Quad Output, Intelligent Integrated Power Management for IoT Applications.
Proceedings of the 34th International Conference on VLSI Design and 20th International Conference on Embedded Systems, 2021

2019
Analysis and Design of Cyclic Switched-Capacitor DC-DC Converters.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Analysis and Design of a Multi-Step Bias-Flip Rectifier for Piezoelectric Energy Harvesting.
IEEE J. Solid State Circuits, 2019

2018
A 1.2 pJ/cycle KHz Timer Circuit for Heavily Duty-Cycled Systems.
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

Multi-Step Bias-Flip Rectification for Piezoelectric Energy Harvesting.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

2015
8.3 A 10.5μA/MHz at 16MHz single-cycle non-volatile memory access microcontroller with full state retention at 108nA in a 90nm process.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2013
A 40nm 650Mhz 0.5fJ/Bit/Search TCAM Compiler Using Complementary Bit-cell Architecture.
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

2011
Design and technology interaction beyond 32nm.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2009
An enhanced topology for reliability of a high performance 3.3V I/O buffer in a single-well bulk CMOS 1.8v-oxide low voltage process.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

2008
A Robust Level-Shifter Design for Adaptive Voltage Scaling.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

2007
A low-power 333Mbps mobile-double data rate output driver with adaptive feedback to minimize overshoots and undershoots.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

2005
A high performance, high voltage output buffer in a low voltage CMOS process.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2003
Optimization of 1.8V I/O circuits for performance, reliability at the 100nm technology node.
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

1997
Signal compression through spatial frequency-based motion estimation.
Integr., 1997

1996
Spatial frequency based motion estimation for image sequence compression.
Proceedings of the 3rd International Conference on High Performance Computing, 1996


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