Vinod K. Agarwal

Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

Invited Talk: Embedded Test for Systems-on-a-Chip.

[BibT_eX]

[DOI]

Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

1998

Diagnosis of clustered faults and wafer testing.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

Correct Diagnosis of Almost All Faulty Units in a Multiprocessor System.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 1998

1997

Embedded Test and Measurement Critical for Deep Submicron Technology.

[BibT_eX]

[DOI]

Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997

1995

A Diagnosis Algorithm for Constant Degree Structures and Its Application to VLSI Circuit Testing.

[BibT_eX]

[DOI]

Laurence E. LaForge

IEEE Trans. Parallel Distributed Syst., 1995

Fast signature computation for BIST linear compactors.

[BibT_eX]

[DOI]

D. Lambidonis

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

A quasi-optimal scheduling of intermediate signatures for multiple signature analysis compaction testing schemes.

[BibT_eX]

[DOI]

J. Electron. Test., 1995

VTS 1994 Panel Report on BIST for Consumer Products.

[BibT_eX]

IEEE Des. Test Comput., 1995

A Specification-Driven Architectural Design Environment.

[BibT_eX]

[DOI]

Computer, 1995

Distributed Probabilistic Diagnosis of MCMs on Large Area.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

1994

Almost Sure Diagnosis of Almost Every Good Element.

[BibT_eX]

[DOI]

Laurence E. LaForge

IEEE Trans. Computers, 1994

Diagnosis of t/(t+1)-Diagnosable Systems.

[BibT_eX]

[DOI]

SIAM J. Comput., 1994

Performance of Interconnection Network in Multithreaded Architectures.

[BibT_eX]

[DOI]

Shashank S. Nemawarkar

Ramaswamy Govindarajan

Proceedings of the PARLE '94: Parallel Architectures and Languages Europe, 1994

VAMP: A Hierarchical Framework for Design for Manufacturability.

[BibT_eX]

[DOI]

Morie E. Malowany

Gordon W. Roberts

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

A Comparative Study of Multiprocessor List Scheduling Heuristics.

[BibT_eX]

Proceedings of the 27th Annual Hawaii International Conference on System Sciences (HICSS-27), 1994

DASE: An Environment for System Level Telecommunication Design Exploration and Modelling.

[BibT_eX]

[DOI]

Proceedings of the Computer Aided System Theory, 1994

1993

Multiprocessor Fault Diagnosis Under Local Constraints.

[BibT_eX]

[DOI]

K. B. Lakshmanan

IEEE Trans. Computers, 1993

Distributed Fault diagnosis of a Ring of Processors.

[BibT_eX]

[DOI]

K. B. Lakshmanan

Parallel Process. Lett., 1993

Built-In Self-Diagnosis for Repairable Embedded RAMs.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 1993

Analysis of Multithreaded Multiprocessors with Distributed Shared Memory.

[BibT_eX]

[DOI]

Shashank S. Nemawarkar

Ramaswamy Govindarajan

Proceedings of the Fifth IEEE Symposium on Parallel and Distributed Processing, 1993

The design of a library support system for a telecommunication system synthesis environment.

[BibT_eX]

[DOI]

Proceedings of the Fourth International Workshop on Rapid System Prototyping, 1993

Fault Location Algorithms for Repairable Embedded.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics, 1993

A Novel Methodology Using Genetic Algorithms for the Design of Caches and Cache Replacement Policy.

[BibT_eX]

Erik R. Altman

Proceedings of the 5th International Conference on Genetic Algorithms, 1993

1992

Computing the probability of undetected error for shortened cyclic codes.

[BibT_eX]

[DOI]

IEEE Trans. Commun., 1992

Using an asymmetric error model to study aliasing in signature analysis registers.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

BIST of PCB interconnects using boundary-scan architecture.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

Distributed Diagnosis Algorithms for Regular Interconnected Structures.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1992

A system level synthesis framework for computer architectures.

[BibT_eX]

[DOI]

Proceedings of the Third International Workshop on Rapid System Prototyping, 1992

Performance Evaluation of Latency Tolerant Architectures.

[BibT_eX]

Shashank S. Nemawarkar

Ramaswamy Govindarajan

Proceedings of the Computing and Information, 1992

Wafer Testing with Pairwise Comparisons.

[BibT_eX]

[DOI]

Laurence E. LaForge

Proceedings of the Digest of Papers: FTCS-22, 1992

1991

Iterative algorithms for computing aliasing probabilities.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

Diagnosis of T/S-Diagnosable Systems.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 1991

Fast Signature Computation for Linear Compactors.

[BibT_eX]

[DOI]

D. Lambidonis

Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

1990

Optimizing error masking in BIST by output data modification.

[BibT_eX]

[DOI]

Yervant Zorian

J. Electron. Test., 1990

Serial Interfacing for Embedded-Memory Testing.

[BibT_eX]

[DOI]

Benoit Nadeau-Dostie

Allan Silburt

IEEE Des. Test Comput., 1990

A new procedure for weighted random built-in self-test.

[BibT_eX]

[DOI]

Fidel Muradali

Benoit Nadeau-Dostie

Proceedings of the Proceedings IEEE International Test Conference 1990, 1990

1989

An analysis of the probabilistic behavior of linear feedback signature registers.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989

On the Complexity of Single Fault Set Diagnosability and Diagnosis Problems.

[BibT_eX]

[DOI]

David Avis

IEEE Trans. Computers, 1989

t/s-Diagnosable Systems: A Characterization and Diagnosis Algorithm.

[BibT_eX]

[DOI]

K. B. Lakshmanan

Proceedings of the Graph-Theoretic Concepts in Computer Science, 1989

: Experiments on Aliasing in Signature Analysis Registers.

[BibT_eX]

[DOI]

Proceedings of the Proceedings International Test Conference 1989, 1989

Testing of Glue Logic Interconnects Using Boundary Scan Architecture.

[BibT_eX]

[DOI]

Proceedings of the Proceedings International Test Conference 1989, 1989

A diagnosis method using pseudo-random vectors without intermediate signatures.

[BibT_eX]

[DOI]

Robert C. Aitken

Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

Distributed syndrome decoding for regular interconnected structures.

[BibT_eX]

[DOI]

Proceedings of the Nineteenth International Symposium on Fault-Tolerant Computing, 1989

1988

Dynamic testability measures for ATPG.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988

A Reconfiguration Scheme for Yield Enhancement of Large Area Binary Tree Architectures.

[BibT_eX]

[DOI]

Michael C. Howells

IEEE Trans. Computers, 1988

Testing and Diagnosis of Interconnects Using Boundary Scan Architecture.

[BibT_eX]

[DOI]

Abu S. M. Hassan

Janusz Rajski

Proceedings of the Proceedings International Test Conference 1988, 1988

On Multiple Fault Coverage and Aliasing Probability Measures.

[BibT_eX]

[DOI]

Proceedings of the Proceedings International Test Conference 1988, 1988

Aliasing probability of non-exhaustive randomized syndrome tests.

[BibT_eX]

[DOI]

Robert C. Aitken

Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

An iterative technique for calculating aliasing probability of linear feedback signature registers.

[BibT_eX]

[DOI]

Proceedings of the Eighteenth International Symposium on Fault-Tolerant Computing, 1988

1987

A New Built-In Self-Test Design for PLA's with High Fault Coverage and Low Overhead.

[BibT_eX]

[DOI]

Hideo Fujiwara

IEEE Trans. Computers, 1987

A Generalized Theory for System Level Diagnosis.

[BibT_eX]

[DOI]

David Avis

IEEE Trans. Computers, 1987

Testing and Applications of Inverter-Free PLAs.

[BibT_eX]

[DOI]

Janusz Rajski

IEEE Des. Test, 1987

1986

McBOOLE: A New Procedure for Exact Logic Minimization.

[BibT_eX]

[DOI]

Michel R. Dagenais

Nicholas C. Rumin

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1986

A Fault-Tolerant Modular Architecture for Binary Trees.

[BibT_eX]

[DOI]

A. S. Mahmudul Hassan

IEEE Trans. Computers, 1986

A Theory for the Design of Soft-Error-Tolerant VLSI Circuits.

[BibT_eX]

[DOI]

IEEE J. Sel. Areas Commun., 1986

Testability Measures : What Do They Do for ATPG ?

[BibT_eX]

Proceedings of the Proceedings International Test Conference 1986, 1986

1985

An Efficient Unsorted VLSI Dictionary Machine.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1985

Implementing a Built-In Self-Test PLA Design.

[BibT_eX]

[DOI]

Hideo Fujiwara

IEEE Des. Test, 1985

Testing Properties and Applications of Inverter-Free PLA's.

[BibT_eX]

Janusz Rajski

Proceedings of the Proceedings International Test Conference 1985, 1985

The McBOOLE logic minimizer.

[BibT_eX]

[DOI]

Michel R. Dagenais

Nicholas C. Rumin

Proceedings of the 22nd ACM/IEEE conference on Design automation, 1985

1984

Data Flow Anomaly Detection.

[BibT_eX]

[DOI]

Jacek Jachner

IEEE Trans. Software Eng., 1984

Higher Certainty of Error Coverage by Output Data Modification.

[BibT_eX]

Yervant Zorian

Proceedings of the Proceedings International Test Conference 1984, 1984

A Design for Machines with Built-In Tolerance to Soft Errors.

[BibT_eX]

Proceedings of the Proceedings International Test Conference 1984, 1984

An Efficient VLSI Dictionary Machine.

[BibT_eX]

[DOI]

Proceedings of the 11th Annual Symposium on Computer Architecture, 1984

1983

Non-Stuck-At Fault Detection in nMOS Circuits by Region Analysis.

[BibT_eX]

Michael G. Lamoureux

Proceedings of the Proceedings International Test Conference 1983, 1983

1981

Multiple Fault Testing of Large Circuits by Single Fault Test Sets.

[BibT_eX]

[DOI]

Andy S. F. Fung

IEEE Trans. Computers, 1981

1980

Generic Fault Characterizations for Table Look-Up Coverage Bounding.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1980

Multiple Fault Detection in Programmable Logic Arrays.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1980

A microprocessor based tea dryer controller.

[BibT_eX]

[DOI]

S. S. S. P. Rao

Proceedings of the 3rd ACM SIGSMALL symposium and the first SIGPC symposium on Small systems, 1980

1979

A Functional Form Approach to Test Set Coverage in Tree Networks.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1979

Recursive Coverage Projection of Test Sets.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1979

1977

Resolution-Oriented Fault Interrelationships in Combinational Logic Networks.

[BibT_eX]

[DOI]