Vinicius Callegaro

According to our database, Vinicius Callegaro authored at least 18 papers between 2010 and 2019.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2019

Four-Level Forms for Memristive Material Implication Logic.

Felipe S. Marranghello, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas

IEEE Trans. Very Large Scale Integr. Syst., 2019

2018

A Simple and Effective Heuristic Method for Threshold Logic Identification.

Augusto Neutzling, Mayler G. A. Martins, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

2016

Graph-Based Transistor Network Generation Method for Supergate Design.

Vinicius Neves Possani, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas, Felipe de Souza Marques, Leomar Soares da Rosa Jr.

IEEE Trans. Very Large Scale Integr. Syst., 2016

2015

Factored Forms for Memristive Material Implication Stateful Logic.

Felipe S. Marranghello, Vinicius Callegaro, Mayler G. A. Martins, André Inácio Reis, Renato P. Ribas

IEEE J. Emerg. Sel. Topics Circuits Syst., 2015

Improved logic synthesis for memristive stateful logic using multi-memristor implication.

Felipe S. Marranghello, Vinicius Callegaro, Mayler G. A. Martins, André Inácio Reis, Renato P. Ribas

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

SOP based logic synthesis for memristive IMPLY stateful logic.

Felipe S. Marranghello, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Bottom-up disjoint-support decomposition based on cofactor and boolean difference analysis.

Vinicius Callegaro, Felipe S. Marranghello, Mayler G. A. Martins, Renato P. Ribas, André Inácio Reis

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

2013

Improving the methodology to build non-series-parallel transistor arrangements.

Vinicius N. Possani, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas, Felipe S. Marques, Leomar S. da Rosa Jr.

Proceedings of the 26th Symposium on Integrated Circuits and Systems Design, 2013

Read-polarity-once Boolean functions.

Vinicius Callegaro, Mayler G. A. Martins, Renato P. Ribas, André Inácio Reis

Proceedings of the 26th Symposium on Integrated Circuits and Systems Design, 2013

Transistor-level optimization of CMOS complex gates.

Vinicius N. Possani, Felipe S. Marques, Leomar S. da Rosa Jr., Vinicius Callegaro, André Inácio Reis, Renato P. Ribas

Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013

Iterative remapping respecting timing constraints.

Lucas Machado, Mayler G. A. Martins, Vinicius Callegaro, Renato P. Ribas, André Inácio Reis

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

Efficient transistor-level design of CMOS gates.

Vinicius N. Possani, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas, Felipe de Souza Marques, Leomar Soares da Rosa Jr.

Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

2012

NSP kernel finder - A methodology to find and to build non-series-parallel transistor arrangements.

Vinicius N. Possani, Felipe S. Marques, Leomar S. da Rosa Jr., Vinicius Callegaro, André Inácio Reis, Renato P. Ribas

Proceedings of the 25th Symposium on Integrated Circuits and Systems Design, 2012

KL-cut based digital circuit remapping.

Lucas Machado, Mayler G. A. Martins, Vinicius Callegaro, Renato P. Ribas, André Inácio Reis

Proceedings of the NORCHIP 2012, Copenhagen, Denmark, November 12-13, 2012, 2012

2011

Contributions to the evaluation of ensembles of combinational logic gates.

Renato P. Ribas, Simone Bavaresco, N. Schuch, Vinicius Callegaro, Marcelo Lubaszewski, André Inácio Reis

Microelectron. J., 2011

Area impact analysis of via-configurable regular fabric for digital integrated circuit design.

Vinícius Dal Bem, Paulo F. Butzen, Carlos Eduardo Klock, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas

Proceedings of the 24th Symposium on Integrated Circuits and Systems Design, 2011

Efficient method to compute minimum decision chains of Boolean functions.

Mayler G. A. Martins, Vinicius Callegaro, Renato P. Ribas, André Inácio Reis

Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

2010

SwitchCraft: a framework for transistor network design.

Vinicius Callegaro, Felipe de Souza Marques, Carlos Eduardo Klock, Leomar Soares da Rosa Jr., Renato P. Ribas, André Inácio Reis

Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, 2010