Vineet Wason

According to our database1, Vineet Wason authored at least 4 papers between 2004 and 2007.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

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Bibliography

2007
An Efficient Uncertainty- and Skew-aware Methodology for Clock Tree Synthesis and Analysis.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

2005
A probabilistic framework for power-optimal repeater insertion in global interconnects under parameter variations.
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

2004
A probabilistic framework to estimate full-chips subthreshold leakage power distribution considering within-die and die-to-die P-T-V variations.
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004

Simultaneous optimization of supply and threshold voltages for low-power and high-performance circuits in the leakage dominant era.
Proceedings of the 41th Design Automation Conference, 2004


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