Vineesh V. S.

According to our database, Vineesh V. S. authored at least 8 papers between 2017 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2022

Aries: A Semiformal Technique for Fine-Grained Bug Localization in Hardware Designs.

Binod Kumar, V. S. Vineesh, Puneet Nemade, Masahiro Fujita

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

2021

Enhanced Design Debugging With Assistance From Guidance-Based Model Checking.

V. S. Vineesh, Binod Kumar, Rushikesh Shinde, Neelam Sharma, Masahiro Fujita, Virendra Singh

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Enhancing Testbench Quality via Genetic Algorithm.

Harsh Bhargav, Vineesh V. S., Binod Kumar, Virendra Singh

Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021

2020

Analyzing Hardware Security Properties of Processors through Model Checking.

Binod Kumar, Akshay Kumar Jaiswal, V. S. Vineesh, Rushikesh Shinde

Proceedings of the 33rd International Conference on VLSI Design and 19th International Conference on Embedded Systems, 2020

LUT-based Circuit Approximation with Targeted Error Guarantees.

Vinod G. U, Vineesh V. S., Jaynarayan T. Tudu, Masahiro Fujita, Virendra Singh

Proceedings of the 29th IEEE Asian Test Symposium, 2020

2019

Identification of Effective Guidance Hints for Better Design Debugging by Formal Methods.

V. S. Vineesh, Binod Kumar, Jay Adhaduk

Proceedings of the VLSI Design and Test - 23rd International Symposium, 2019

Orion: A Technique to Prune State Space Search Directions for Guidance-Based Formal Verification.

Vineesh V. S., Binod Kumar, Rushikesh Shinde, Akshay Jaiswal, Harsh Bhargava, Virendra Singh

Proceedings of the 28th IEEE Asian Test Symposium, 2019

2017

Achieving full functional coverage for the forwarding unit of pipelined processors.

V. S. Vineesh, Nihar Hage, B. Karthik, Virendra Singh

Proceedings of the 2017 IEEE East-West Design & Test Symposium, 2017