Vincenzo Chironi

According to our database1, Vincenzo Chironi authored at least 11 papers between 2008 and 2015.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
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PhD thesis 
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Links

Online presence:

On csauthors.net:

Bibliography

2015
A -19dBm sensitivity integrated RF-DC converter with regulated output voltage for powering UHF wireless sensors.
Proceedings of the 6th International Workshop on Advances in Sensors and Interfaces, 2015

A 5.8-13 GHz SDR RF front-end for wireless sensors network robust to out-of-band interferers in 65nm CMOS.
Proceedings of the 6th International Workshop on Advances in Sensors and Interfaces, 2015

2014
Non-idealities Compensation in Full-Digital Receivers with Application to Ultra-Wide Band.
Wirel. Pers. Commun., 2014

A SAW-less dual-band RF front-end for IR-UWB receiver in 65nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013
A Digitally Modulated Class-E Polar Amplifier in 90 nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

A 32-channel 12-bits single slope A-to-D converter for LHC environment.
Proceedings of 2013 International Conference on IC Design & Technology, 2013

A dual-band balun LNA resilient to 5-6 GHz WLAN blockers for IR-UWB in 65nm CMOS.
Proceedings of 2013 International Conference on IC Design & Technology, 2013

2011
An impedance modulated class-E polar amplifier in 90 nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

2010
An area efficient digital amplitude modulator in 90nm CMOS.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A compact digital amplitude modulator in 90nm CMOS.
Proceedings of the Design, Automation and Test in Europe, 2010

2008
An 820μW 9b 40MS/s Noise-Tolerant Dynamic-SAR ADC in 90nm Digital CMOS.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008


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