Vincent De Heyn

According to our database, Vincent De Heyn authored at least 13 papers between 2001 and 2018.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2018

Sequential 3D: Key integration challenges and opportunities for advanced semiconductor scaling.

A. Vandooren, Liesbeth Witters, Jacopo Franco, Arindam Mallik, Bertrand Parvais, Z. Wu, Amey Walke, V. Deshpande, E. Rosseel, Andriy Hikavyy, W. Li, L. Peng, Nouredine Rassoul, Geraldine Jamieson, Fumihiro Inoue, G. Verbinnen, Katia Devriendt, Lieve Teugels, N. Heylen, E. Vecchio, T. Zheng, Niamh Waldron, Vincent De Heyn, Dan Mocuta, Nadine Collaert

Proceedings of the 2018 International Conference on IC Design & Technology, 2018

2008

Advanced Planar Bulk and Multigate CMOS Technology: Analog-Circuit Benchmarking up to mm-Wave Frequencies.

Piet Wambacq, Abdelkarim Mercha, Karen Scheir, Bob Verbruggen, Jonathan Borremans, Vincent De Heyn, Steven Thijs, Dimitri Linten, Geert Van der Plas, Bertrand Parvais, Morin Dehan, Stefaan Decoutere, Charlotte Soens, Nadine Collaert, Malgorzata Jurczak

Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2007

The Potential of FinFETs for Analog and RF Circuit Applications.

Piet Wambacq, Bob Verbruggen, Karen Scheir, Jonathan Borremans, Morin Dehan, Dimitri Linten, Vincent De Heyn, Geert Van der Plas, Abdelkarim Mercha, Bertrand Parvais, Cedric Gustin, Vaidyanathan Subramanian, Nadine Collaert, Malgorzata Jurczak, Stefaan Decoutere

IEEE Trans. Circuits Syst. I Regul. Pap., 2007

A CMOS Ultra-Wideband Receiver for Low Data-Rate Communication.

Julien Ryckaert, Marian Verhelst, Mustafa Badaroglu, Stefano D'Amico, Vincent De Heyn, Claude Desset, Pierluigi Nuzzo, Bart van Poucke, Piet Wambacq, Andrea Baschirotto, Wim Dehaene, Geert Van der Plas

IEEE J. Solid State Circuits, 2007

A 0.65-to-1.4 nJ/Burst 3-to-10 GHz UWB All-Digital TX in 90 nm CMOS for IEEE 802.15.4a.

Julien Ryckaert, Geert Van der Plas, Vincent De Heyn, Claude Desset, Bart van Poucke, Jan Craninckx

IEEE J. Solid State Circuits, 2007

A 0.65-to-1.4nJ/burst 3-to-10GHz UWB Digital TX in 90nm CMOS for IEEE 802.15.4a.

Julien Ryckaert, Geert Van der Plas, Vincent De Heyn, Claude Desset, Geert Vanwijnsberghe, Bart van Poucke, Jan Craninckx

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

A fast start-up 3GHz-10GHz digitally controlled oscillator for UWB impulse radio in 90nm CMOS.

Vincent De Heyn, Geert Van der Plas, Julien Ryckaert, Jan Craninckx

Proceedings of the 33rd European Solid-State Circuits Conference, 2007

2006

Analog-Digital Partitioning for Low-Power UWB Impulse Radios under CMOS Scaling.

Mustafa Badaroglu, Claude Desset, Julien Ryckaert, Vincent De Heyn, Geert Van der Plas, Piet Wambacq, Bart van Poucke

EURASIP J. Wirel. Commun. Netw., 2006

A 16mA UWB 3-to-5GHz 20Mpulses/s Quadrature Analog Correlation Receiver in 0.18µm CMOS.

Julien Ryckaert, Mustafa Badaroglu, Vincent De Heyn, Geert Van der Plas, Pierluigi Nuzzo, Andrea Baschirotto, Stefano D'Amico, Claude Desset, Hans Suys, Michael Libois, Bart van Poucke, Piet Wambacq, Bert Gyselinckx

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2005

Ultra-wide-band transmitter for low-power wireless body area networks: design and evaluation.

Julien Ryckaert, Claude Desset, Andrew Fort, Mustafa Badaroglu, Vincent De Heyn, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Bart van Poucke, Bert Gyselinckx

IEEE Trans. Circuits Syst. I Regul. Pap., 2005

2003

High frequency characterization and modelling of the parasitic RC performance of two terminal ESD CMOS protection devices.

Vesselin K. Vassilev, Snezana Jenei, Guido Groeseneken, Rafael Venegas, Steven Thijs, Vincent De Heyn, M. Natarajan Iyer, Michiel Steyaert, Herman E. Maes

Microelectron. Reliab., 2003

2002

Significance of the failure criterion on transmission line pulse testing.

Bart Keppens, Vincent De Heyn, M. Natarajan Iyer, Vesselin K. Vassilev, Guido Groeseneken

Microelectron. Reliab., 2002

2001

Influence of gate length on ESD-performance for deep submicron CMOS technology.

Karlheinz Bock, Bart Keppens, Vincent De Heyn, Guido Groeseneken, L. Y. Ching, A. Naem

Microelectron. Reliab., 2001