Vincent C. Gaudet
Orcid: 0000-0002-5534-0825Affiliations:
- University of Waterloo, Canada
According to our database1,
Vincent C. Gaudet
authored at least 83 papers
between 1998 and 2022.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
-
on orcid.org
On csauthors.net:
Bibliography
2022
J. Signal Process. Syst., 2022
Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022
2021
Hierarchical Subspace Learning for Dimensionality Reduction to Improve Classification Accuracy in Large Data Sets.
Proceedings of the 51st IEEE International Symposium on Multiple-Valued Logic, 2021
Proceedings of the International Joint Conference on Neural Networks, 2021
Proceedings of the 12th International Conference on Information, 2021
2020
Acceleration of Large Margin Metric Learning for Nearest Neighbor Classification Using Triplet Mining and Stratified Sampling.
CoRR, 2020
Tackling Imputation Across Time Series Models Using Deep Learning and Ensemble Learning.
Proceedings of the 2020 IEEE International Conference on Systems, Man, and Cybernetics, 2020
Machine Learning Based Approaches for Imputation in Time Series Data and their Impact on Forecasting.
Proceedings of the 2020 IEEE International Conference on Systems, Man, and Cybernetics, 2020
Proceedings of the IEEE International Conference on Image Processing, 2020
Proceedings of the Image Analysis and Recognition - 17th International Conference, 2020
2019
Proceedings of the 2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL), 2019
2018
Proceedings of the 2018 IEEE Intelligent Vehicles Symposium, 2018
Efficient Hardware Realization of Convolutional Neural Networks Using Intra-Kernel Regular Pruning.
Proceedings of the 48th IEEE International Symposium on Multiple-Valued Logic, 2018
2017
Proceedings of the 47th IEEE International Symposium on Multiple-Valued Logic, 2017
2016
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016
A Survey and Tutorial on Contemporary Aspects of Multiple-Valued Logic and Its Application to Microelectronic Circuits.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the 28th International Conference on Microelectronics, 2016
2015
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015
Proceedings of the 49th Annual Conference on Information Sciences and Systems, 2015
Proceedings of the 53rd Annual Allerton Conference on Communication, 2015
Proceedings of the 49th Asilomar Conference on Signals, Systems and Computers, 2015
2014
Clockless Stochastic Decoding of Low-Density Parity-Check Codes: Architecture and Simulation Model.
J. Signal Process. Syst., 2014
High-Throughput Low-Energy Self-Timed CAM Based on Reordered Overlapped Search Mechanism.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
A 167-ps 2.34-mW Single-Cycle 64-Bit Binary Tree Comparator With Constant-Delay Logic in 65-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
IEICE Trans. Inf. Syst., 2014
Proceedings of the 2014 IEEE Workshop on Signal Processing Systems, 2014
Proceedings of the IEEE 44th International Symposium on Multiple-Valued Logic, 2014
Adaptive dual-threshold neural signal compression suitable for implantable recording.
Proceedings of the IEEE International Conference on Acoustics, 2014
Proceedings of the 48th Annual Conference on Information Sciences and Systems, 2014
2013
Log-Domain Arithmetic for High-Speed Fuzzy Control on a Field-Programmable Gate Array.
Proceedings of the Soft Computing: State of the Art Theory and Novel Applications, 2013
IEEE Trans. Circuits Syst. I Regul. Pap., 2013
IEICE Electron. Express, 2013
Lowering Error Floors in Stochastic Decoding of LDPC Codes Based on Wire-Delay Dependent Asynchronous Updating.
Proceedings of the 43rd IEEE International Symposium on Multiple-Valued Logic, 2013
Proceedings of the 47th Annual Conference on Information Sciences and Systems, 2013
2012
J. Signal Process. Syst., 2012
Design of a Low Power, Inductorless Wideband Variable-Gain Amplifier for High-Speed Receiver Systems.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012
IEEE Trans. Circuits Syst. I Regul. Pap., 2012
Proceedings of the 2012 IEEE Workshop on Signal Processing Systems, 2012
Proceedings of the 2012 IEEE Workshop on Signal Processing Systems, 2012
Proceedings of the 2012 IEEE Workshop on Signal Processing Systems, 2012
Proceedings of the 42nd IEEE International Symposium on Multiple-Valued Logic, 2012
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
High-Throughput Low-Energy Content-Addressable Memory Based on Self-Timed Overlapped Search Mechanism.
Proceedings of the 18th IEEE International Symposium on Asynchronous Circuits and Systems, 2012
2011
IEEE Trans. Circuits Syst. I Regul. Pap., 2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Proceedings of the 45st Annual Conference on Information Sciences and Systems, 2011
2010
IEEE Trans. Very Large Scale Integr. Syst., 2010
IEEE Trans. Signal Process., 2010
Proceedings of the 40th IEEE International Symposium on Multiple-Valued Logic, 2010
Implementation of enhanced CDMA utilizing low complexity joint detection with iterative processing.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
2009
Analog DFT Processors for OFDM Receivers: Circuit Mismatch and System Performance Analysis.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009
A Compact 1.1-Gb/s Encoder and a Memory-Based 600-Mb/s Decoder for LDPC Convolutional Codes.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009
High-Throughput Bit-Serial LDPC Decoder LSI Based on Multiple-Valued Asynchronous Interleaving.
IEICE Trans. Electron., 2009
Proceedings of the ISMVL 2009, 2009
An Asynchronous Programmable Parallel 2-D Image Filter CMOS Ic Based on the Gilbert Vector Multiplier.
Proceedings of the BIODEVICES 2009, 2009
2008
IEEE Trans. Circuits Syst. II Express Briefs, 2008
Integr., 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Current-mode memory cell with power down phase for discrete time analog iterative decoders.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
2007
IEEE Trans. Circuits Syst. II Express Briefs, 2007
Inductive ESD Protection For Narrow Band and Ultra-Wideband CMOS Low Noise Amplifiers.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
2006
IEEE Trans. Circuits Syst. I Regul. Pap., 2006
IEEE Trans. Circuits Syst. II Express Briefs, 2006
An Examination of the Effect of Feature Size Scaling on Effective Power Consumption in Analog to Digital Converters.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
2005
IEEE Trans. Circuits Syst. II Express Briefs, 2005
Proceedings of the NETWORKING 2005: Networking Technologies, 2005
Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 2005
Proceedings of the 2005 IEEE International Symposium on Information Theory, 2005
Proceedings of the 2005 IEEE International Symposium on Information Theory, 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
2004
Short-cycle-free interleaver design for increasing minimum squared Euclidean distance.
Proceedings of the 2004 IEEE International Symposium on Information Theory, 2004
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
2003
IEEE J. Solid State Circuits, 2003
1998
J. Circuits Syst. Comput., 1998