Vinayaka Jyothi

Orcid: 0000-0002-6735-3121

According to our database1, Vinayaka Jyothi authored at least 9 papers between 2011 and 2018.

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Bibliography

2018
DPFEE: A High Performance Scalable Pre-Processor for Network Security Systems.
IEEE Trans. Multi Scale Comput. Syst., 2018

2017
Fingerprinting Field Programmable Gate Arrays.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

TAINT: Tool for Automated INsertion of Trojans.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

2016
BRAIN: BehavioR Based Adaptive Intrusion Detection in Networks: Using Hardware Performance Counters to Detect DDoS Attacks.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

FPGA Trust Zone: Incorporating trust and reliability into FPGA designs.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

2015
Deep Packet Field Extraction Engine (DPFEE): A pre-processor for network intrusion detection and denial-of-service detection systems.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

2014
Intra-die process variation aware anomaly detection in FPGAs.
Proceedings of the 2014 International Test Conference, 2014

2011
Design and analysis of ring oscillator based Design-for-Trust technique.
Proceedings of the 29th IEEE VLSI Test Symposium, 2011

Blue team red team approach to hardware trust assessment.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011


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